公开(公告)号：US10366931B2

公开(公告)日：2019-07-30

申请号：US16133850

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Cheng Chi ,  Pietro Montanini ,  Tenko Yamashita ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/8238 ,  H01L27/092

Abstract: This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.

公开(公告)号：US10263099B2

公开(公告)日：2019-04-16

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/51

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US10170591B2

公开(公告)日：2019-01-01

申请号：US15178871

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US10170585B2

公开(公告)日：2019-01-01

申请号：US15437840

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/285 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/3105

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US10157827B2

公开(公告)日：2018-12-18

申请号：US15196371

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L23/522 ,  H01L29/417 ,  H01L23/528 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L27/12 ,  H01L29/66

Abstract: A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity.

公开(公告)号：US20180240889A1

公开(公告)日：2018-08-23

申请号：US15437840

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105

CPC classification number: H01L29/6656 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US20180174855A1

公开(公告)日：2018-06-21

申请号：US15890859

申请日：2018-02-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US09887133B2

公开(公告)日：2018-02-06

申请号：US15623758

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/45 ,  H01L27/088 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/45

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

公开(公告)号：US20170358662A1

公开(公告)日：2017-12-14

申请号：US15178871

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US09837402B1

公开(公告)日：2017-12-05

申请号：US15170109

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Cheng Chi

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105 ,  H01L29/08 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/66795

Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.