公开(公告)号：US10510662B2

公开(公告)日：2019-12-17

申请号：US15805282

申请日：2017-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L21/76 ,  H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3105

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

公开(公告)号：US10297672B2

公开(公告)日：2019-05-21

申请号：US15649227

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Seong Yeol Mun ,  Kwan-Yong Lim ,  Kijik Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28 ,  H01L21/02 ,  H01L29/49

Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.

公开(公告)号：US10290738B2

公开(公告)日：2019-05-14

申请号：US15483476

申请日：2017-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Kwan-Yong Lim

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L21/223 ,  H01L29/165 ,  H01L29/167

Abstract: One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.

公开(公告)号：US20190139892A1

公开(公告)日：2019-05-09

申请号：US15805282

申请日：2017-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

公开(公告)号：US10163900B2

公开(公告)日：2018-12-25

申请号：US15427403

申请日：2017-02-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Kwan-Yong Lim

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311

Abstract: Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

公开(公告)号：US20180294348A1

公开(公告)日：2018-10-11

申请号：US15483476

申请日：2017-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Kwan-Yong Lim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/265 ,  H01L21/225 ,  H01L21/223 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L21/2236 ,  H01L21/2256 ,  H01L21/26513 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795

Abstract: One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.

公开(公告)号：US20180090391A1

公开(公告)日：2018-03-29

申请号：US15274974

申请日：2016-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mira Park ,  Kwan-Yong Lim ,  Steven Bentley ,  Amitabh Jain

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/223 ,  H01L21/324

CPC classification number: H01L21/823892 ,  H01L21/2236 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

公开(公告)号：US09842933B1

公开(公告)日：2017-12-12

申请号：US15180422

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Kwan-Yong Lim ,  Steven John Bentley ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/306 ,  H01L21/265 ,  H01L27/24 ,  H01L29/78

CPC classification number: H01L29/78618 ,  H01L21/265 ,  H01L21/30604 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/7926 ,  H01L2029/7858

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20170301776A1

公开(公告)日：2017-10-19

申请号：US15132383

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Steven J. Bentley ,  Kwan-Yong Lim

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/311 ,  H01L21/28 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.

公开(公告)号：US20170278844A1

公开(公告)日：2017-09-28

申请号：US15082242

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L27/088 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.