公开(公告)号：US09263324B2

公开(公告)日：2016-02-16

申请号：US14080562

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  Troy L. Graves-Abe

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.

Abstract translation: 可以形成TSV，其具有通过顶部衬底表面形成的顶部截面，以及通过底部衬底表面形成的底部截面。 顶部截面可以具有对应于设计规则的最小横截面，并且顶部截面深度可对应于可工作的纵横比。 顶部通孔可以被填充或插入，以便可以继续顶部处理。 底部通孔可以具有更大的横截面，以便于形成穿过其中的导电路径。 底部部分通孔从顶部部分通孔的背面延伸到底部，并且在基板变薄之后形成。 可以通过在从接合的顶部和底部部分通孔去除牺牲填充材料之后形成导电路径来完成TSV。

公开(公告)号：US09257361B2

公开(公告)日：2016-02-09

申请号：US14532437

申请日：2014-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  Emily Kinser ,  JoAnn M. Rolick-DiGiacomio ,  Charu Tejwani

IPC: H01L21/44 ,  H01L23/38 ,  H01L23/367 ,  F25B21/02 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L23/38 ,  F25B21/02 ,  F25B2321/02 ,  H01L23/367 ,  H01L23/481 ,  H01L27/0688 ,  H01L2224/13

Abstract: Methods and structures for thermoelectric cooling of 3D semiconductor structures are disclosed. Thermoelectric vias (TEVs) to form a thermoelectric cooling structure. The TEVs are formed with an etch process similar to that used in forming electrically active through-silicon vias (TSVs). However, the etched cavities are filled with materials that exhibit the thermoelectric effect, instead of a conductive metal as with a traditional electrically active TSV. The thermoelectric materials are arranged such that when a voltage is applied to them, the thermoelectric cooling structure carries heat away from the interior of the structure from the junction where the thermoelectric materials are electrically connected.

公开(公告)号：US10103119B2

公开(公告)日：2018-10-16

申请号：US15420362

申请日：2017-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Tanya A. Atanasova

IPC: H01L23/00

Abstract: The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. The method may include: forming a metallic pillar over a substrate, the metallic pillar having an upper surface; forming a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and forming a solder material over the upper surface of the metallic pillar within and constrained by the wetting inhibitor layer.

公开(公告)号：US10096557B2

公开(公告)日：2018-10-09

申请号：US15791568

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ekta Misra ,  Mukta G. Farooq ,  Krishna Tunga

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/3205

Abstract: Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

公开(公告)号：US10068899B2

公开(公告)日：2018-09-04

申请号：US15239976

申请日：2016-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ian D. W. Melville ,  Mukta G. Farooq

IPC: H01L27/06 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.

公开(公告)号：US10037911B2

公开(公告)日：2018-07-31

申请号：US15692666

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US20180108607A1

公开(公告)日：2018-04-19

申请号：US15292721

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Ian D. W. Melville

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76841 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53276

Abstract: An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.

公开(公告)号：US09929085B2

公开(公告)日：2018-03-27

申请号：US15171320

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Mukta G. Farooq ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/40

Abstract: One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.

公开(公告)号：US20180005873A1

公开(公告)日：2018-01-04

申请号：US15692666

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US20170352618A1

公开(公告)日：2017-12-07

申请号：US15171320

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Mukta G. Farooq ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/40

Abstract: One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.