公开(公告)号：US10515679B2

公开(公告)日：2019-12-24

申请号：US15889369

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.

公开(公告)号：US10453750B2

公开(公告)日：2019-10-22

申请号：US15629884

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej J. Pawlak ,  Guillaume Bouche ,  Ajey P. Jacob

IPC: H01L25/07 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775

Abstract: Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

公开(公告)号：US10374106B2

公开(公告)日：2019-08-06

申请号：US15486849

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob

IPC: G02B6/12 ,  H01L31/18 ,  H01L27/144 ,  H01L31/105 ,  H01L31/0232 ,  H01L31/0352 ,  H01L31/0392

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.

公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US20190058087A1

公开(公告)日：2019-02-21

申请号：US15680977

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob ,  Srinivasa Banna ,  Deepak Nayak

IPC: H01L33/24 ,  H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/46 ,  H01L33/36 ,  H01L27/15

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.

公开(公告)号：US09812393B2

公开(公告)日：2017-11-07

申请号：US14867341

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Suraj K. Patil ,  Min-hwa Chi

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US09754843B1

公开(公告)日：2017-09-05

申请号：US15205535

申请日：2016-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Ajey P. Jacob

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L27/092 ,  H01L29/49 ,  H01L21/302 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L21/823885 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

公开(公告)号：US09691497B2

公开(公告)日：2017-06-27

申请号：US14867331

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi ,  Ajey P. Jacob

IPC: G11C17/16 ,  H01L23/525 ,  H01L29/78 ,  H01L29/06

CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L29/0673 ,  H01L29/785

Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.

公开(公告)号：US09614058B2

公开(公告)日：2017-04-04

申请号：US14860276

申请日：2015-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

公开(公告)号：US09240342B2

公开(公告)日：2016-01-19

申请号：US13944200

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Jody Fronheiser ,  Witold P. Maszara

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/32055 ,  H01L21/3105 ,  H01L21/76224 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66765 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a stable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 104 defects/cm2 or less throughout its entire height. In another case, a metastable replacement fin is grown to a height that is greater than an unconfined metastable critical thickness of the replacement fin material and it has a defect density of 105 defects/cm2 or less throughout at least 90% of its entire height.

Abstract translation: 本文公开了用于形成处于稳定或亚稳态的替代翅片材料的各种方法。 在一种情况下，稳定的替换翅片生长到比替换翅片材料的无约束的稳定的临界厚度大的高度，并且其整个高度的缺陷密度为104个缺陷/ cm2或更小。 在另一种情况下，亚稳替代鳍生长到高于替代翅片材料的无约束亚稳临界厚度的高度，并且在其整个高度的至少90％中具有105缺陷/ cm2或更小的缺陷密度。