公开(公告)号：US20080122103A1

公开(公告)日：2008-05-29

申请号：US11564358

申请日：2006-11-29

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

摘要翻译： 提供的互连，其包括具有顶表面和下表面的铜导体，其中帽形成在金属导体的顶表面上。 盖由双层叠或多层薄膜形成，层压膜包括超紫（UV）阻挡膜和扩散阻挡膜。 扩散阻挡膜和UV阻挡膜可以通过中间膜分离。

公开(公告)号：US09685404B2

公开(公告)日：2017-06-20

申请号：US13348011

申请日：2012-01-11

申请人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

发明人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L23/522 ,  H01H85/02

CPC分类号： H01L23/5256 ,  H01H2085/0275 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

公开(公告)号：US09059169B2

公开(公告)日：2015-06-16

申请号：US13165087

申请日：2011-06-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01L21/26 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/768 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.

摘要翻译： 提供线后端的电熔丝结构（BEOL）互连和制造方法。 该方法包括在衬底中与第一底层金属线对齐形成互连通孔，并在衬底中形成电熔丝通孔，露出第二下面的金属线。 该方法还包括用第二底层金属线形成缺陷并用金属填充互连通孔并与第一底层金属线接触，从而形成互连结构。 该方法还包括用金属填充e熔丝通孔并与缺陷和第二下面的金属线接触，从而形成电熔丝结构。

公开(公告)号：US08912658B2

公开(公告)日：2014-12-16

申请号：US12915510

申请日：2010-10-29

申请人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

发明人： Ronald Filippi ,  Ping-Chuan Wang ,  Griselda Bonilla ,  Kaushik Chanda ,  Robert D. Edwards ,  Andrew H. Simon

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

摘要翻译： 一种改进的互连结构，其包括具有嵌入其中的导电特征的介电层，所述导电特征具有与介电层的第二顶表面基本共面的第一顶表面; 金属盖层直接位于第一顶表面上，其中金属盖层基本上不延伸到第二顶表面上; 位于所述第二顶表面上的第一电介质盖层，其中所述第一电介质盖层基本上不延伸到所述第一顶表面上，并且所述第一电介质盖层比所述金属盖层厚; 以及金属盖层和第一电介质盖层上的第二电介质盖层。 还提供了形成互连结构的方法。

公开(公告)号：US20130302978A1

公开(公告)日：2013-11-14

申请号：US13605763

申请日：2012-09-06

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76835 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

摘要翻译： 提供了包括位于铜结构的暴露表面上的石墨烯盖的互连结构。 在一些实施例中，石墨烯盖仅位于铜结构的最上表面的顶部，而在其它实施例中，石墨烯盖位于垂直侧壁和铜结构的最上表面的顶部。 铜结构位于电介质材料内。

公开(公告)号：US20130299988A1

公开(公告)日：2013-11-14

申请号：US13468693

申请日：2012-05-10

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76835 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

摘要翻译： 提供了包括位于铜结构的暴露表面上的石墨烯盖的互连结构。 在一些实施例中，石墨烯盖仅位于铜结构的最上表面的顶部，而在其它实施例中，石墨烯盖位于垂直侧壁和铜结构的最上表面的顶部。 铜结构位于电介质材料内。

公开(公告)号：US20130175697A1

公开(公告)日：2013-07-11

申请号：US13344009

申请日：2012-01-05

申请人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Satyanarayana V. Nitta

发明人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Satyanarayana V. Nitta

IPC分类号： H01L23/538 ,  H01L21/31 ,  B32B9/04

CPC分类号： H01L23/5384 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249969 ,  H01L2924/00

摘要： A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

摘要翻译： 一种电介质堆叠和使用单步沉积工艺将叠层沉积到衬底的方法。 电介质堆叠包括具有不同组成原子百分比，密度和孔隙率的相同元素化合物的致密层和多孔层。 该堆叠增强机械模量强度并增强氧化和铜扩散阻挡性能。 电介质叠层在整个网络中具有无机或杂化的无机 - 有机随机三维共价键，其含有不同化学组成的不同区域，例如与相同类型材料的低k组分相邻但具有较高孔隙率的盖组分 。

公开(公告)号：US08470706B2

公开(公告)日：2013-06-25

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20110227232A1

公开(公告)日：2011-09-22

申请号：US12724903

申请日：2010-03-16

申请人： Griselda Bonilla ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.

摘要翻译： 用于形成齿形导体的方法和具有齿形导体的器件包括在介电层上形成硬掩模层，并对硬掩模层进行构图。 使用硬掩模层在电介质层中蚀刻沟槽，使得沟槽具有沿着沟槽的长度交替的较浅部分和较深部分。 导体沉积在沟槽中，使得形成具有沿着导电线的长度周期性地设置的不同深度的锯齿形导电线。

公开(公告)号：US20110108990A1

公开(公告)日：2011-05-12

申请号：US12613551

申请日：2009-11-06

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  Chih-Chao Yang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  David L. Rath ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  Chih-Chao Yang

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.

摘要翻译： 一种封盖线的方法包括通过选择性沉积工艺在铜线上形成金属膜层，铜线设置在电介质基底中，其中沉积还导致杂散金属材料沉积在介质基片的表面上， 并用各向同性蚀刻工艺进行蚀刻以除去电介质基底表面上的金属膜层和杂散金属材料的一部分，其中金属膜层以足以使金属膜层盖保持在其上的初始厚度沉积 铜线除去杂散金属材料。