公开(公告)号：US20210066116A1

公开(公告)日：2021-03-04

申请号：US17006642

申请日：2020-08-28

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/06

Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.

公开(公告)号：US20200328122A1

公开(公告)日：2020-10-15

申请号：US16843706

申请日：2020-04-08

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66

Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.

公开(公告)号：US20190198643A1

公开(公告)日：2019-06-27

申请号：US16220361

申请日：2018-12-14

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Anabela Veloso ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L29/66666 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a vertical channel device and a method of fabricating the same. According to one aspect, a method for fabricating a vertical channel device includes forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate. The semiconductor layer stack includes an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer. Forming the vertical semiconductor structure includes: etching the upper semiconductor layer to form the upper portion and the intermediate semiconductor layer to form the intermediate portion, detecting whether the etching has reached the lower semiconductor layer, and in response to detecting that the etching has reached the lower semiconductor layer, changing to a modified etching chemistry being different from an etching chemistry used during the etching of the intermediate semiconductor layer, and etching the lower semiconductor layer using the modified etching chemistry to form the lower portion. The modified etching chemistry is such that the lower portion is formed to present, along at least a part of the lower portion, a lateral dimension gradually increasing along a direction towards the substrate. The method further comprises forming a gate stack extending vertically along the intermediate portion to define a channel region of the vertical channel device.

公开(公告)号：US10090393B2

公开(公告)日：2018-10-02

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

公开(公告)号：US20180182868A1

公开(公告)日：2018-06-28

申请号：US15845300

申请日：2017-12-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Silvia Armini ,  Elisabeth Camerotto ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

公开(公告)号：US09899220B2

公开(公告)日：2018-02-20

申请号：US15289550

申请日：2016-10-10

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Zheng Tao ,  Arjun Singh ,  Jan Doise

IPC: H01L21/00 ,  H01L21/033

CPC classification number: H01L21/0338 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.

公开(公告)号：US20170170017A1

公开(公告)日：2017-06-15

申请号：US15289550

申请日：2016-10-10

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Zheng Tao ,  Arjun Singh ,  Jan Doise

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.

公开(公告)号：US09520291B2

公开(公告)日：2016-12-13

申请号：US14757671

申请日：2015-12-23

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Kaidong Xu

IPC: H01L21/306 ,  H01L21/225 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/308 ,  H01L21/266 ,  H01L21/84

CPC classification number: H01L21/2253 ,  H01L21/225 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3085 ,  H01L21/31144 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/845

Abstract: According to an aspect of the present inventive concept there is provided a method of providing an implanted region in a semiconductor structure including a first region and a second region, the method comprising: providing a first implantation mask covering the first region of the semiconductor structure, the first implantation mask including a first sacrificial layer, wherein the first sacrificial layer is formed as a spin-on-carbon (SOC) layer, and a second sacrificial layer, wherein the second sacrificial layer is formed as a spin-on-glass (SOG) layer; subjecting the semiconductor structure to an ion implantation process wherein an extension of the first implantation mask is such that ion implantation in the first region is counteracted and ion implantation in the second region is allowed wherein the second region is implanted; forming a third sacrificial layer covering the second region of the semiconductor structure, wherein the third sacrificial layer includes carbon; removing the second sacrificial layer at the first region by etching, wherein the third sacrificial layer protects the second region from being affected by said etching; and removing the first sacrificial layer at the first region and the third sacrificial layer at the second region by etching.

Abstract translation: 根据本发明构思的一个方面，提供了一种在包括第一区域和第二区域的半导体结构中提供注入区域的方法，所述方法包括：提供覆盖半导体结构的第一区域的第一注入掩模， 所述第一注入掩模包括第一牺牲层，其中所述第一牺牲层形成为自旋碳（SOC）层，以及第二牺牲层，其中所述第二牺牲层形成为旋涂玻璃（spin-on-glass） SOG）层; 对所述半导体结构进行离子注入工艺，其中所述第一注入掩模的延伸使得抵消所述第一区域中的离子注入并且允许在所述第二区域中的离子注入，其中所述第二区域被注入; 形成覆盖半导体结构的第二区域的第三牺牲层，其中第三牺牲层包括碳; 通过蚀刻去除第一区域处的第二牺牲层，其中第三牺牲层保护第二区域免受所述蚀刻的影响; 以及通过蚀刻在第一区域和第二区域去除第一牺牲层。