公开(公告)号：US20210091025A1

公开(公告)日：2021-03-25

申请号：US17023538

申请日：2020-09-17

Applicant: Infineon Technologies AG

Inventor： Gert Pfahl ,  Daniel Bolowski ,  Marian Sebastian Broll ,  Michael Kreuz ,  Evelyn Napetschnig ,  Holger Schulze ,  Stefan Woehlert

IPC: H01L23/00 ,  C22C21/10 ,  C22C21/16 ,  C22C21/02

Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.

公开(公告)号：US10930614B2

公开(公告)日：2021-02-23

申请号：US15659670

申请日：2017-07-26

Applicant: Infineon Technologies AG

Inventor： Manfred Mengel ,  Alexander Heinrich ,  Steffen Orso ,  Thomas Behrens ,  Oliver Eichinger ,  Lim Fong ,  Evelyn Napetschnig ,  Edmund Riedl

IPC: H01L23/00 ,  B23K35/30 ,  B23K35/26 ,  B23K35/28 ,  C22C13/00 ,  C22C18/00 ,  C22C18/04 ,  C22C30/04 ,  C22C30/06 ,  H01L23/488 ,  H01L23/495 ,  B23K1/00

Abstract: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

公开(公告)号：US10741402B2

公开(公告)日：2020-08-11

申请号：US15692495

申请日：2017-08-31

Applicant: Infineon Technologies AG

Inventor： Paul Frank ,  Gretchen Adema ,  Thomas Bertaud ,  Michael Ehmann ,  Eric Graetz ,  Kamil Karlovsky ,  Evelyn Napetschnig ,  Werner Robl ,  Tobias Schmidt ,  Joachim Seifert ,  Frank Wagner ,  Stefan Woehlert

IPC: H01L23/00 ,  H01L21/285 ,  H01L29/861

Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

公开(公告)号：US20190148233A1

公开(公告)日：2019-05-16

申请号：US16248255

申请日：2019-01-15

Applicant: Infineon Technologies AG

Inventor： Karl Mayer ,  Evelyn Napetschnig ,  Michael Pinczolits ,  Michael Sternad ,  Michael Roesner

IPC: H01L21/78 ,  H01L23/00

Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

公开(公告)号：US10115688B2

公开(公告)日：2018-10-30

申请号：US14726078

申请日：2015-05-29

Applicant: Infineon Technologies AG

Inventor： Kamil Karlovsky ,  Evelyn Napetschnig ,  Michael Ehmann ,  Mark Harrison ,  Anton Pugatschow

IPC: H01L21/44 ,  H01L23/00

Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

公开(公告)号：US20160351516A1

公开(公告)日：2016-12-01

申请号：US14726078

申请日：2015-05-29

Applicant: Infineon Technologies AG

Inventor： Kamil Karlovsky ,  Evelyn Napetschnig ,  Michael Ehmann ,  Mark Harrison ,  Anton Pugatschow

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05599 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

Abstract translation: 半导体器件包括设置在衬底的半导体表面上的接触金属层，设置在接触金属层上的扩散阻挡层，设置在扩散阻挡层上的惰性层和设置在惰性层上的焊料层。

公开(公告)号：US20150228607A1

公开(公告)日：2015-08-13

申请号：US14692815

申请日：2015-04-22

Applicant: Infineon Technologies AG

Inventor： Tobias Schmidt ,  Evelyn Napetschnig ,  Franz Stueckler ,  Anton Pugatschow ,  Mark Harrison

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/29082 ,  H01L2224/32227 ,  H01L2224/83805 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.

Abstract translation: 在各种实施例中，提供层叠。 层叠可以包括载体; 设置在载体上的第一金属; 设置在所述第一金属上的第二金属; 以及设置在第二金属上方的焊料材料或提供与由外部源供应的焊料的接触的材料。 第二金属可以具有至少1800℃的熔融温度，并且在焊接工艺期间和焊接工艺之后至少一个焊料材料中不会或基本上不溶解。