公开(公告)号：US10373839B2

公开(公告)日：2019-08-06

申请号：US14023577

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Friedrich Kroener ,  Ingo Muri

IPC: H01L21/3063 ,  H01L21/67

Abstract: A wafer contacting device may include: a receiving region configured to receive a wafer; and an elastically deformable carrier disposed in the receiving region and including an electrically conductive surface region.

公开(公告)号：US20170338153A1

公开(公告)日：2017-11-23

申请号：US15596961

申请日：2017-05-16

Applicant: Infineon Technologies AG

Inventor： Johannes Baumgartl ,  Manfred Engelhardt ,  Oliver Hellmund ,  Iris Moder ,  Ingo Muri

IPC: H01L21/78 ,  H01L29/06 ,  H01L21/306 ,  H01L21/304 ,  H01L21/683 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/82 ,  H01L23/528 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/861 ,  H01L2221/68327

Abstract: A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor wafer towards a second lateral surface of the semiconductor wafer. The method further includes filling a portion of the plurality of trenches with filler material. The method further includes thinning the semiconductor wafer from the second lateral surface of the semiconductor wafer to form a thinned semiconductor wafer. The method further includes forming a back side metallization layer structure on a plurality of semiconductor chip regions of the semiconductor wafer after thinning the semiconductor wafer. The method further includes removing a part of the filler material from the plurality of trenches after forming the back side metallization layer structure to obtain the plurality of semiconductor devices.

公开(公告)号：US09683306B2

公开(公告)日：2017-06-20

申请号：US14467106

申请日：2014-08-25

Applicant: Infineon Technologies AG

Inventor： Friedrich Kroener ,  Ingo Muri

IPC: C25D15/00 ,  C25D5/02 ,  C25D5/18 ,  C25D5/34 ,  C25D17/00 ,  C25D5/10 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  C25D21/10

CPC classification number: C25D15/00 ,  C25D3/12 ,  C25D3/38 ,  C25D3/46 ,  C25D3/48 ,  C25D5/02 ,  C25D5/022 ,  C25D5/10 ,  C25D5/18 ,  C25D5/34 ,  C25D17/00 ,  C25D17/001 ,  C25D21/10

Abstract: A method of forming a composite material is provided. The method may include: arranging a suspension in physical contact with a carrier, wherein the suspension may comprise an electrolyte and a plurality of particles of a first component of the composite material; causing the particles of the first component of the composite material to sediment on the carrier, wherein a plurality of spaces may be formed between the sedimented particles; and forming by electroplating a second component of the composite material from the electrolyte in at least a fraction of the plurality of spaces.

公开(公告)号：US20150068918A1

公开(公告)日：2015-03-12

申请号：US14023577

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Friedrich Kroener ,  Ingo Muri

IPC: H01L21/3063 ,  H01L21/67

CPC classification number: H01L21/3063 ,  H01L21/67075 ,  H01L21/67086

Abstract: A wafer contacting device may include: a receiving region configured to receive a wafer; and an elastically deformable carrier disposed in the receiving region and including an electrically conductive surface region.

Abstract translation: 晶片接触装置可以包括：被配置为接收晶片的接收区域; 以及设置在所述接收区域中并且包括导电表面区域的可弹性变形的载体。

公开(公告)号：US11552048B2

公开(公告)日：2023-01-10

申请号：US17101339

申请日：2020-11-23

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Barbara Eichinger ,  Thorsten Meyer ,  Ingo Muri

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

公开(公告)号：US20220310380A1

公开(公告)日：2022-09-29

申请号：US17841781

申请日：2022-06-16

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

公开(公告)号：US20210391377A1

公开(公告)日：2021-12-16

申请号：US17345534

申请日：2021-06-11

Applicant: Infineon Technologies AG

Inventor： Alexander Frey ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri ,  Alfred Sigl ,  Tobias Weindler

IPC: H01L27/146 ,  H01L23/544 ,  H01L21/304 ,  H01L29/78 ,  G01S17/894

Abstract: A method of manufacturing a semiconductor device is described. The method includes providing a semiconductor substrate. The semiconductor substrate includes a high-doped semiconductor substrate layer, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer. The high-doped semiconductor substrate layer is removed, wherein the removing includes dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer. Further, the low-doped semiconductor etch stop layer is thinned to generate an exposed surface of the high-doped semiconductor device layer.

公开(公告)号：US20210391218A1

公开(公告)日：2021-12-16

申请号：US17343885

申请日：2021-06-10

Applicant: Infineon Technologies AG

Inventor： Felix Johannes Heinrich Ernst ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/225 ,  H01L29/06 ,  H01L23/14

Abstract: A method of manufacturing a semiconductor device is described. A semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate layer and a semiconductor device layer. The method includes transforming areas of the semiconductor device layer into dicing areas which can be removed by etching, and removing the semiconductor substrate layer and the dicing areas by using etching.

公开(公告)号：US10714377B2

公开(公告)日：2020-07-14

申请号：US16122456

申请日：2018-09-05

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Bernhard Goller ,  Iris Moder ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L29/861 ,  H01L21/306 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L29/32 ,  H01L21/02 ,  H01L21/66 ,  H01L23/00 ,  H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L21/266 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.

公开(公告)号：US20190074212A1

公开(公告)日：2019-03-07

申请号：US16122456

申请日：2018-09-05

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Bernhard Goller ,  Iris Moder ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/66 ,  H01L21/02 ,  H01L29/06 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.