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公开(公告)号：US20160163674A1
公开(公告)日：2016-06-09
申请号：US15044021
申请日：2016-02-15
发明人： Ulrich Wachter , Dominic Maier , Thomas Kilger
IPC分类号： H01L23/00
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L21/76838 , H01L23/31 , H01L23/3114 , H01L23/48 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/48 , H01L24/85 , H01L2224/02317 , H01L2224/02331 , H01L2224/02379 , H01L2224/03462 , H01L2224/0347 , H01L2224/03828 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05008 , H01L2224/05147 , H01L2224/05548 , H01L2224/05553 , H01L2224/05655 , H01L2224/1132 , H01L2224/1134 , H01L2224/11849 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2924/00014 , H01L2924/10161 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2224/03 , H01L2224/11 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
摘要翻译： 集成电路通过将多个半导体管芯放置在支撑衬底上而被封装，每个半导体管芯在面向支撑衬底的一侧具有多个端子，并用模制化合物覆盖半导体管芯以形成模制结构。 然后将支撑基板从模制结构中取出，以使端子露出半导体管芯的一侧，并且在模制结构上形成金属再分布层，并与半导体管芯和模塑料的端子直接接触。 形成再分配层，而不用半导体管芯的端子在模制结构的一侧形成电介质层。 还公开了相应的模制基板和单独的模制半导体封装。
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公开(公告)号：US09041505B2
公开(公告)日：2015-05-26
申请号：US14024395
申请日：2013-09-11
发明人： Gottfried Beer , Urs Elrod , Christiane Brunner , Thomas Kilger
CPC分类号： H01F27/2804 , H01F41/041 , H01F2027/2819 , H01L23/49816 , H01L23/49822 , H01L23/645 , H01L24/19 , H01L2224/12105 , Y10T29/4902 , Y10T29/49071
摘要： In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.
摘要翻译： 根据实施例，变压器包括设置在第一电介质层的第一侧上的第一导电层中的第一线圈和设置在第一电介质层的第二侧上的第二导电层中的第二线圈。 每个线圈具有设置在其相应线圈内部的第一端和设置在其相应线圈的外周边的第二端。 设置在第二导电层中的第一交叉直接连接到第一线圈的第一端并延伸超过第一线圈的外周。 此外，设置在第一导电层中的第二交叉直接连接到第二线圈的第一端并且延伸超过第二线圈的外周。
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公开(公告)号：US20150091171A1
公开(公告)日：2015-04-02
申请号：US14043138
申请日：2013-10-01
发明人： Ulrich Wachter , Dominic Maier , Thomas Kilger
IPC分类号： H01L21/56 , H01L23/48 , H01L21/768 , H01L23/31
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L21/76838 , H01L23/31 , H01L23/3114 , H01L23/48 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/48 , H01L24/85 , H01L2224/02317 , H01L2224/02331 , H01L2224/02379 , H01L2224/03462 , H01L2224/0347 , H01L2224/03828 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05008 , H01L2224/05147 , H01L2224/05548 , H01L2224/05553 , H01L2224/05655 , H01L2224/1132 , H01L2224/1134 , H01L2224/11849 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2924/00014 , H01L2924/10161 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2224/03 , H01L2224/11 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
摘要翻译： 集成电路通过将多个半导体管芯放置在支撑衬底上而被封装，每个半导体管芯在面向支撑衬底的一侧具有多个端子，并用模制化合物覆盖半导体管芯以形成模制结构。 然后将支撑基板从模制结构中取出，以使端子露出半导体管芯的一侧，并且在模制结构上形成金属再分布层，并与半导体管芯和模塑料的端子直接接触。 形成再分配层，而不用半导体管芯的端子在模制结构的一侧形成电介质层。 还公开了相应的模制基板和单独的模制半导体封装。
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34.发明授权Method of packaging integrated circuits and a molded substrate with non-functional placeholders embedded in a molding compound 有权封装集成电路的方法和嵌入模塑料中的非功能性占位符的模塑基材公开(公告)号：US08828807B1
公开(公告)日：2014-09-09
申请号：US13944260
申请日：2013-07-17
发明人： Ulrich Wachter , Dominic Maier , Thomas Kilger
CPC分类号： B81C1/00301 , B81B7/007 , B81B2201/0257 , H01L21/568 , H01L23/48 , H01L23/552 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H03H9/1064 , H04R19/005 , H01L2924/00
摘要： A method of packaging integrated circuits includes providing a molded substrate including a first plurality of functional semiconductor dies and a plurality of placeholders laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the placeholders. The exposed placeholders are removed to form cavities in the molded substrate. A second plurality of functional semiconductor dies is inserted in the cavities formed in the molded substrate. Electrical connections are formed to the first plurality and second plurality of functional semiconductor dies at a side of the dies uncovered by the molding compound.
摘要翻译： 包装集成电路的方法包括提供包括第一多个功能性半导体管芯和多个占位符的模制基板，所述第一多个功能半导体管芯和横向间隔开并由模制化合物覆盖的多个占位符。 模塑料被稀释以暴露至少一些占位符。 暴露的占位符被移除以在模塑基底中形成空腔。 将第二多个功能半导体管芯插入形成在模制基板中的空腔中。 在由模制化合物未覆盖的模具的一侧上形成电连接到第一多个和第二多个功能半导体模具。
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公开(公告)号：US20140239438A1
公开(公告)日：2014-08-28
申请号：US13774541
申请日：2013-02-22
发明人： Thomas Kilger , Ulrich Wachter , Dominic Maier , Gottfried Beer
IPC分类号： H01L23/538 , H01L27/04 , H01L21/82
CPC分类号： H01L21/561 , H01L21/568 , H01L21/78 , H01L21/82 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/50 , H01L27/04 , H01L28/00 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/24137 , H01L2224/2518 , H01L2224/73267 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/15311 , H01L2924/19105 , H01L2924/00
摘要： A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
摘要翻译： 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。
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