公开(公告)号：US20200051743A1

公开(公告)日：2020-02-13

申请号：US16606130

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Feras EID ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN ,  Kristof DARMAWIKARTA

IPC: H01G4/14 ,  H05K1/02 ,  H05K1/03

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. The capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes.

公开(公告)号：US20190355647A1

公开(公告)日：2019-11-21

申请号：US16527961

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L21/027 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20190311916A1

公开(公告)日：2019-10-10

申请号：US16317789

申请日：2016-07-14

Applicant: Intel Corporation

Inventor： Sri Chaitra CHAVALI ,  Siddharth K. ALUR ,  Amanda E. SCHUCKMAN ,  Amruthavalli Palla ALUR ,  Islam A. SALAMA ,  Yikang DENG ,  Kristof DARMAWIKARTA

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimageable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

公开(公告)号：US20190206786A1

公开(公告)日：2019-07-04

申请号：US15857454

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Sandeep GAAN ,  Srinivas V. PIETAMBARAM ,  Sameer R. PAITAL

IPC: H01L23/50 ,  H01L23/498 ,  H01L49/02 ,  H01L23/64 ,  H01L21/48

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L23/49822 ,  H01L28/20 ,  H01L28/40

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first surface, one or more second conductive contacts on a second surface opposite the first surface, a dielectric layer between the first and the second surfaces, and an embedded capacitor on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded capacitor comprises a first metal layer on the dielectric layer, a thin film dielectric material on a surface of the metal layer, a second metal layer on the surface of the first metal layer, and a third metal layer on the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250125275A1

公开(公告)日：2025-04-17

申请号：US18999978

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Adel A. ELSHERBINI ,  Kristof DARMAWIKARTA ,  Robert A. MAY ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240304536A1

公开(公告)日：2024-09-12

申请号：US18120172

申请日：2023-03-10

Applicant: Intel Corporation

Inventor： Sanjay THARMARAJAH ,  Kristof DARMAWIKARTA

IPC: H01L23/498 ,  H01L23/532

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16227

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a substrate layer, and a plurality of traces on the substrate layer. In an embodiment, each of the plurality of traces are covered on sidewalls and an entire top surface by a first layer. In an embodiment, a pad is on the substrate layer, where the pad is covered on sidewalls and an entire top surface by a second layer.

公开(公告)号：US20240176167A1

公开(公告)日：2024-05-30

申请号：US18071246

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Tolga ACIKALIN ,  Harel FRISH ,  Sandeep GAAN ,  John HECK ,  Eric J. M. MORET ,  Suddhasattwa NAD ,  Haisheng RONG

IPC: G02F1/01 ,  G02B6/125

CPC classification number: G02F1/0113 ,  G02B6/125 ,  G02F1/0147 ,  G02B2006/12145

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core where the core comprises glass. In an embodiment, the package substrate further comprises an optical waveguide over the core, and an optical phase change material over the optical waveguide.

公开(公告)号：US20240105575A1

公开(公告)日：2024-03-28

申请号：US17953206

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Jason M. GAMBA ,  Haifa HARIRI ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Kyle MCELHINNY ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Haobo CHEN ,  Bai NIE ,  Numair AHMED

IPC: H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.

公开(公告)号：US20230361002A1

公开(公告)日：2023-11-09

申请号：US17738085

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Samuel GEORGE ,  Srinivas PIETAMBARAM

IPC: H01L23/48 ,  H01L23/15 ,  H01L21/48 ,  H01L21/68

CPC classification number: H01L23/481 ,  H01L23/15 ,  H01L21/486 ,  H01L21/68

Abstract: The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

公开(公告)号：US20230140389A1

公开(公告)日：2023-05-04

申请号：US18091781

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Adel A. ELSHERBINI ,  Kristof DARMAWIKARTA ,  Robert A. MAY ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.