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    SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES
    31.
    发明申请
    SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20210202377A1

    公开(公告)日：2021-07-01

    申请号：US16727747

    申请日：2019-12-26

    Applicant: Intel Corporation

    Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

    SELECTIVE RECESS OF INTERCONNECTS FOR PROBING HYBRID BOND DEVICES
    32.
    发明申请
    SELECTIVE RECESS OF INTERCONNECTS FOR PROBING HYBRID BOND DEVICES 有权

    公开(公告)号：US20210175192A1

    公开(公告)日：2021-06-10

    申请号：US16703298

    申请日：2019-12-04

    Applicant: Intel Corporation

    Inventor： Brennen K. Mueller ,  Adel Elsherbini ,  Mauro Kobrinsky ,  Johanna Swan ,  Shawna Liff ,  Pooya Tadayon

    IPC: H01L23/00

    Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

    TRANSISTOR CHANNEL PASSIVATION WITH 2D CRYSTALLINE MATERIAL
    33.
    发明申请
    TRANSISTOR CHANNEL PASSIVATION WITH 2D CRYSTALLINE MATERIAL 有权

    公开(公告)号：US20210083122A1

    公开(公告)日：2021-03-18

    申请号：US16570965

    申请日：2019-09-13

    Applicant: Intel Corporation

    Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

    IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

    Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

    Scalable interconnect structures with selective via posts
    36.
    发明授权
    Scalable interconnect structures with selective via posts 有权
    具有选择性通孔的可扩展互连结构

    公开(公告)号：US09391019B2

    公开(公告)日：2016-07-12

    申请号：US14220814

    申请日：2014-03-20

    Applicant: Intel Corporation

    Inventor： Mauro Kobrinsky ,  Tatyana Andryushchenko ,  Ramanan Chebiam ,  Hui Jae Yoo

    IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.

    Abstract translation: 互连结构，包括设置在下层互连特征的顶表面上的选择通孔，以及选择性地形成这种柱的制造技术。 以下实施例中，可以独立于通孔开口中的配准误差来维持最小互连线间距。 在实施例中，选择性通孔支柱的底部横向尺寸小于通孔开口的底部横向尺寸，在该通孔开口内设置有支柱。 导电通孔的形成可优先于由通孔开口暴露的下互连特征的顶表面。 随后沉积的电介质材料回填了超过互连特征的通孔开口的部分，其中没有形成导电通孔。 上级互连功能着陆在选择性通孔上以与较低级别特征电互连。

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