公开(公告)号：US11574851B2

公开(公告)日：2023-02-07

申请号：US16287116

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Omkar Karhade ,  Ram Viswanath ,  Je-Young Chang ,  Weihua Tang ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L25/18 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US20220397726A1

公开(公告)日：2022-12-15

申请号：US17344213

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Tolga Acikalin ,  Sushrutha Gujjula ,  Kelly Lofgreen ,  Ravindranath Mahajan ,  Chia-pin Chiu

IPC: G02B6/42 ,  F21V8/00

Abstract: An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate and a photonic integrated circuit device attached thereto, wherein the package substrate includes a heat dissipation structure disposed therein. A back surface of the photonic integrated circuit device may thermally coupled to the heat dissipation structure within the package substrate for the removal of heat from the photonic integrated circuit device, which allows for access to an active surface of the photonic integrated circuit device for the attachment of fiber optic cables and eliminates the need for a heat dissipation device to be thermally attached to the active surface of the photonic integrated circuit device.

公开(公告)号：US11222877B2

公开(公告)日：2022-01-11

申请号：US15721235

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Robert L. Sankman ,  Nitin A. Deshpande ,  Mitul Modi ,  Thomas J. De Bonis ,  Robert M. Nickerson ,  Zhimin Wan ,  Haifa Hariri ,  Sri Chaitra J. Chavali ,  Nazmiye Acikgoz Akbay ,  Fadi Y. Hafez ,  Christopher L. Rumer

IPC: H01L25/10 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373 ,  H01L23/42 ,  H01L23/498

Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.

公开(公告)号：US09685421B2

公开(公告)日：2017-06-20

申请号：US14727205

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Ravindranath V Mahajan ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/13 ,  H01L21/683 ,  H01L21/677 ,  H01L21/56 ,  H01L23/15

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67709 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68309 ,  H01L2221/68313 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/8312 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.

公开(公告)号：US20160095220A1

公开(公告)日：2016-03-31

申请号：US14496560

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Nachiket Raravikar

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/28 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/305 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K2201/10734 ,  H05K2203/0191 ,  Y02P70/613 ,  H01L2924/00

Abstract: Some example forms relate to an electronic package. The electronic package includes an electronic component and a substrate that includes a front side and a back side. The electronic component is mounted on the front side of the substrate and conductors are mounted on the back side of the substrate. The substrate is warped due to differences in the coefficients of thermal expansion between the electronic component and the substrate. An adhesive is positioned between the conductors on the back side of the substrate and an adhesive film is attached to the adhesive positioned between the conductors on the back side of the substrate.

Abstract translation: 一些示例形式涉及电子包装。 电子封装包括电子部件和包括正面和背面的基板。 电子部件安装在基板的前侧，导体安装在基板的背面。 由于电子部件和基板之间的热膨胀系数的差异，基板翘曲。 粘合剂位于基板背侧的导体之​​间，并且粘合剂膜附着到位于基板背面的导体之间的粘合剂。

公开(公告)号：US12061371B2

公开(公告)日：2024-08-13

申请号：US17131621

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Nitin Deshpande ,  Omkar Karhade ,  Ravindranath V. Mahajan

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/367 ,  H01L25/16

CPC classification number: G02B6/4292 ,  G02B6/423 ,  G02B6/4243 ,  G02B6/4268 ,  H01L23/3675 ,  H01L24/16 ,  H01L25/167 ,  H01L2224/16145

Abstract: A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

公开(公告)号：US20240063136A1

公开(公告)日：2024-02-22

申请号：US17891560

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Haris Khan Niazi ,  Yi Shi ,  Adel Elsherbini ,  Xavier Brun ,  Georgios Dogiamis ,  Thomas Brown ,  Omkar Karhade

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54473

Abstract: An integrated circuit (IC) device comprises an array comprising rows and columns of conductive interconnect pads. At least one optical alignment fiducial region is distinct from the array and comprises a fiducial pattern, wherein the fiducial pattern comprises a first group of pads contiguous to a second group of pads, and wherein a width of a space between nearest pads of the first and second groups is wider than the spaces between pads within each group.

公开(公告)号：US11804456B2

公开(公告)日：2023-10-31

申请号：US16107791

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Omkar Karhade ,  Martin Rodriguez ,  Gregorio R. Murtagian

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/495 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L23/49582 ,  H01L23/5226 ,  H01L28/10

Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.

公开(公告)号：US11735495B2

公开(公告)日：2023-08-22

申请号：US16287653

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal

IPC: H01L23/46 ,  F28D15/02 ,  H01L21/48 ,  H01L23/427

CPC classification number: H01L23/46 ,  F28D15/02 ,  H01L21/4882 ,  H01L23/427

Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.