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    Interface for storage device access over memory bus
    31.
    发明授权
    Interface for storage device access over memory bus 有权
    通过存储器总线访问存储设备的接口

    公开(公告)号：US09064560B2

    公开(公告)日：2015-06-23

    申请号：US14075765

    申请日：2013-11-08

    Applicant: Intel Corporation

    Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F13/16 ,  G11C7/22

    CPC classification number: G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    Abstract translation: 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。

    Flexible DLL (delay locked loop) calibration
    33.
    发明授权
    Flexible DLL (delay locked loop) calibration 有权

    公开(公告)号：US10381055B2

    公开(公告)日：2019-08-13

    申请号：US14998185

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Shekoufeh Qawami ,  Michael J Allen ,  Rajesh Sundaram

    IPC: G11C7/22 ,  G11C29/02 ,  G11C29/12 ,  G06F13/16

    Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

    Thermal monitoring of memory resources
    35.
    发明授权
    Thermal monitoring of memory resources 有权

    公开(公告)号：US10088880B2

    公开(公告)日：2018-10-02

    申请号：US14837372

    申请日：2015-08-27

    Applicant: Intel Corporation

    Inventor： Rajesh Sundaram ,  Muthukumar P. Swaminathan ,  Doyle Rivers

    IPC: G06F1/20 ,  G06F1/32

    Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.

    TECHNOLOGIES FOR BURST MEMORY WRITE OPERATIONS
    40.
    发明申请
    TECHNOLOGIES FOR BURST MEMORY WRITE OPERATIONS 有权

    公开(公告)号：US20220413740A1

    公开(公告)日：2022-12-29

    申请号：US17357840

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Setul M. Shah ,  Rajesh Sundaram

    IPC: G06F3/06

    Abstract: Techniques for burst memory write operations are disclosed. In the illustrative embodiment, a memory die is limited in how quickly it can perform memory write operations that it receives from a microcontroller due to thermal constraints. The memory die can mitigate the need for the microcontroller to perform a costly rank switch to send an operation to another die by buffering memory write operations. The microcontroller can then send several consecutive memory write operations to a first memory die before switching to a second memory die. The first memory die can then perform the memory write operations while the microcontroller has moved on to other memory operations.

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