公开(公告)号：US11011550B2

公开(公告)日：2021-05-18

申请号：US16461697

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Van Le ,  Abhishek Sharma ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack Kavalieros

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/22 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/49

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

公开(公告)号：US10998302B2

公开(公告)日：2021-05-04

申请号：US16586167

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Van Le ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Min Huang

IPC: H01L25/18 ,  G06F13/40 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L25/075 ,  H01L21/768 ,  H01L25/07 ,  H01L25/04

Abstract: Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.

公开(公告)号：US10659046B2

公开(公告)日：2020-05-19

申请号：US15755021

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rafael Rios ,  Van Le ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H03K19/00 ,  G06F30/30 ,  G06F30/39 ,  G06F1/3203 ,  H01L27/02 ,  H03K19/094

Abstract: A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.

公开(公告)号：US20190393224A1

公开(公告)日：2019-12-26

申请号：US16488231

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Van Le

IPC: H01L27/108 ,  G11C11/408 ,  H01L29/786 ,  H01L23/528 ,  H01L29/24 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  H01L49/02 ,  H01L29/66

Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.

公开(公告)号：US20190355725A1

公开(公告)日：2019-11-21

申请号：US16461697

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Van Le ,  Abhishek Sharma ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack Kavalieros

IPC: H01L27/108 ,  H01L29/22 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

公开(公告)号：US09865684B2

公开(公告)日：2018-01-09

申请号：US14707292

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/267 ,  H01L29/775 ,  H01L29/165 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/308

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

公开(公告)号：US20240332299A1

公开(公告)日：2024-10-03

申请号：US18192601

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Van Le ,  Sudipto Naskar ,  Sukru Yemenicioglu

IPC: H01L27/092

CPC classification number: H01L27/0922

Abstract: An integrated circuit device comprising a plurality of first field effect transistors (FETs) formed on a substrate, wherein a first FET comprises a first channel material comprising a portion of the substrate; and a plurality of second FETs formed on the substrate, wherein a second FET comprises a second channel material that is different from the first channel material, wherein the second channel material comprises a thin film transistor (TFT) channel material.

公开(公告)号：US20240324167A1

公开(公告)日：2024-09-26

申请号：US18189808

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Abhishek Anil Sharma ,  Sukru Yemenicioglu ,  Weimin Han ,  Van Le

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A high performance (HP) thin film transistor (TFT) architecture to enable fabricating backside memory after metallization starts, or as part of back end of line (BEOL) processes. The HP TFT material is suitable for fabricating the memory stack at the lower BEOL temperatures while still delivering the switching speed requirements of a 3D memory stack in the CIM component. A through silicon via (TSV) architecture connects the logic and the memory in the die.

公开(公告)号：US11955560B2

公开(公告)日：2024-04-09

申请号：US16914172

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/66 ,  H01L27/22 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20220253119A1

公开(公告)日：2022-08-11

申请号：US17732792

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G06F1/3203 ,  G06F1/3234 ,  H01L25/16 ,  G06N3/063 ,  H01L25/065 ,  G06F1/20 ,  H01L25/18

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example integrated circuit (IC) package includes a computer processor unit (CPU) die, a memory die, inference engine circuitry within the CPU die, the inference engine circuitry to infer, based on a first machine learning model, a workload for at least one of the CPU die or the memory die, and power management engine circuitry within the CPU die, the power management engine circuitry distinct from the inference engine circuitry, the power management engine circuitry to adjust, based on a second machine learning model different than the first machine learning model, operational parameters associated with the at least one of the CPU die or the memory die, the inferred workload to be an input to the second machine learning model.