公开(公告)号：US11429524B2

公开(公告)日：2022-08-30

申请号：US16785708

申请日：2020-02-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Arvind Kumar ,  Swagath Venkataramani ,  Ching-Tzu Chen

IPC: G06F12/06 ,  G06N3/063

Abstract: Various embodiments are provided for optimized placement of data structures in a hierarchy of memory in a computing environment. One or more data structures may be placed in a first scratchpad memory, a second scratchpad memory, an external memory, or a combination thereof in the hierarchy of memory according to a total memory capacity and bandwidth, a level of reuse of the one or more data structures, a number of operations that use each of the one or more data structures, a required duration each the one or more data structures are required to be placed a first scratchpad or a second scratchpad, and characteristics of those of the one or more data structures competing for placement in the hierarchy of memory that are able to co-exist at a same time step. The second scratchpad memory is positioned between the external memory and the first scratchpad memory at one or more intermediary layers.

公开(公告)号：US20220254995A1

公开(公告)日：2022-08-11

申请号：US17172118

申请日：2021-02-10

Applicant: International Business Machines Corporation

Inventor： JIN PING HAN ,  Philip Joseph Oldiges ,  ROBERT L. BRUCE ,  Ching-Tzu Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

公开(公告)号：US09960345B2

公开(公告)日：2018-05-01

申请号：US15427500

申请日：2017-02-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Ching-Tzu Chen ,  Joel D. Chudow

IPC: H01L43/06 ,  H01L29/06 ,  H01L49/00 ,  H01L29/16 ,  H01L29/24 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/065 ,  G01N27/125 ,  H01L27/22 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/1606 ,  H01L29/24 ,  H01L43/02 ,  H01L43/04 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14 ,  H01L49/003

Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.

公开(公告)号：US20170271602A1

公开(公告)日：2017-09-21

申请号：US15613364

申请日：2017-06-05

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Ching-Tzu Chen ,  Joel D. Chudow

IPC: H01L51/05 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283 ,  H01L29/20 ,  H01L29/66 ,  H01L21/04 ,  H01L51/00 ,  H01L21/441 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L51/0541 ,  G01N27/414 ,  G01N27/4141 ,  G01N27/4146 ,  H01L21/02527 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/02606 ,  H01L21/043 ,  H01L21/283 ,  H01L21/441 ,  H01L21/7682 ,  H01L23/53276 ,  H01L28/60 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/78684 ,  H01L29/78696 ,  H01L43/08 ,  H01L51/0048 ,  H01L51/0558 ,  H01L2221/1094

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.

公开(公告)号：US20160172507A1

公开(公告)日：2016-06-16

申请号：US14571771

申请日：2014-12-16

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Ching-Tzu Chen ,  Joel D. Chudow

IPC: H01L29/786 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283 ,  H01L29/66 ,  H01L29/24 ,  H01L21/04 ,  H01L51/05 ,  H01L51/00 ,  H01L21/441 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L51/0541 ,  G01N27/414 ,  G01N27/4141 ,  G01N27/4146 ,  H01L21/02527 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/02606 ,  H01L21/043 ,  H01L21/283 ,  H01L21/441 ,  H01L21/7682 ,  H01L23/53276 ,  H01L28/60 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/78684 ,  H01L29/78696 ,  H01L43/08 ,  H01L51/0048 ,  H01L51/0558 ,  H01L2221/1094

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.