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    FinFET including varied fin height
    31.
    发明授权
    FinFET including varied fin height 有权
    FinFET包括翅片高度变化

    公开(公告)号：US09324792B1

    公开(公告)日：2016-04-26

    申请号：US14674145

    申请日：2015-03-31

    Applicant: International Business Machines Corporation

    Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu

    IPC: H01L29/06 ,  H01L21/28 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

    CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/7848

    Abstract: According to another embodiment, a semiconductor finFET device includes a semiconductor substrate. The finFET device further includes at least one first semiconductor fin on the semiconductor substrate. The first semiconductor fin comprises a first semiconductor portion extending to a first fin top to define a first height, and a first insulator portion interposed between the first semiconductor portion and the semiconductor substrate. A second semiconductor fin on the semiconductor substrate has a second semiconductor portion extending to a second fin top to define a second height, and a second insulator portion interposed between the second semiconductor portion and the semiconductor substrate, the second height being different from the first height.

    Abstract translation: 根据另一实施例，半导体鳍FETFET器件包括半导体衬底。 finFET器件还包括半导体衬底上的至少一个第一半导体鳍片。 第一半导体鳍片包括延伸到第一鳍片顶部以限定第一高度的第一半导体部分和插入在第一半导体部分和半导体衬底之间的第一绝缘体部分。 半导体衬底上的第二半导体鳍片具有延伸到第二鳍顶部以限定第二高度的第二半导体部分和插入在第二半导体部分和半导体衬底之间的第二绝缘体部分，第二高度不同于第一高度 。

    Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process
    37.
    发明申请
    Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process 审中-公开
    自分散硅化物底板用于EDRAM在CVD / ALD金属工艺中自扩散金属的应用

    公开(公告)号：US20140120687A1

    公开(公告)日：2014-05-01

    申请号：US13665388

    申请日：2012-10-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Cao ,  Sunfei Fang ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

    IPC: H01L21/02

    CPC classification number: H01L27/1087 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/10894 ,  H01L27/1203

    Abstract: In one aspect, a method of fabricating a memory cell capacitor includes the following steps. At least one trench is formed in a silicon wafer. A thin layer of metal is deposited onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy. The metal is removed from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains. The silicon wafer is annealed to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor. A dielectric is deposited into the trench covering the bottom electrode. A top electrode is formed in the trench separated from the bottom electrode by the dielectric.

    Abstract translation: 一方面，制造存储单元电容器的方法包括以下步骤。 在硅晶片中形成至少一个沟槽。 在足以使至少一部分金属自扩散到形成金属的沟槽中暴露的硅晶片的部分中的条件下，使用保形沉积工艺在硅晶片上沉积薄的金属层，衬在沟槽上 半导体合金。 从金属半导体合金选择性的硅晶片中除去金属，使得残留金属 - 半导体合金。 对硅晶片进行退火以使金属 - 半导体合金与硅晶片反应以形成硅化物，其中硅化物用作存储单元电容器的底部电极。 电介质沉积在覆盖底部电极的沟槽中。 在通过电介质从底部电极分离的沟槽中形成顶部电极。

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