公开(公告)号：US20140269004A1

公开(公告)日：2014-09-18

申请号：US14137893

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang

IPC: G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters in the chip package, allowing for heating the memory cells before the programming operations.

Abstract translation: 在远高于工作温度的温度下对阻性存储器结构进行编程可以产生具有更高稳定性的缺陷分布，导致保留时间的潜在改善。 编程温度可高达工作温度100℃。 存储器芯片可以包括芯片封装中的嵌入式加热器，从而允许在编程操作之前加热存储器单元。

公开(公告)号：US20140264747A1

公开(公告)日：2014-09-18

申请号：US14137003

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

Abstract: A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Abstract translation: 电介质层可以实现类似于具有设置在两个电介质层之间的导电层的基极电介质层的结晶取向。 通过提供具有与基底电介质层相似的晶体结构和晶格参数的导电层，晶体取向可以从基极介电层承载在导电层上以影响电介质层。 该方法可以用于形成各向异性介电材料的电容器结构，沿着高介电常数的方向。

公开(公告)号：US08835310B2

公开(公告)日：2014-09-16

申请号：US13725701

申请日：2012-12-21

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

IPC: H01L21/4763 ,  H01L49/02

CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。

公开(公告)号：US20140166107A1

公开(公告)日：2014-06-19

申请号：US13714274

申请日：2012-12-13

Applicant: INTERMOLECULAR, INC.

Inventor： Mankoo Lee ,  Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L31/0264 ,  H01L31/18

CPC classification number: H01L31/056 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/52 ,  Y02E10/541

Abstract: Methods for improving the efficiency of solar cells are disclosed. A solar cell consistent with the present disclosure includes a back contact metal layer disposed on a substrate. The solar cell also includes an electron reflector material(s) layer formed on the back contact metal layer and an absorber material(s) layer disposed on the electron reflector material(s) layer. In addition, the solar cell includes a buffer material(s) layer formed on the absorber material(s) layer wherein the electron reflector material(s) layer, absorber material(s) layer, and buffer material(s) layer form a pn junction within the solar cell. Furthermore, a TCO material(s) layer is formed on the buffer material(s) layer. In addition, the front contact layer is formed on the TCO material(s) layer.

Abstract translation: 公开了提高太阳能电池效率的方法。 符合本公开的太阳能电池包括设置在基板上的背接触金属层。 太阳能电池还包括形成在背接触金属层上的电子反射器材料层和设置在电子反射器材料层上的吸收体材料层。 此外，太阳能电池包括形成在吸收材料层上的缓冲材料层，其中电子反射器材料层，吸收材料层和缓冲材料层形成pn 太阳能电池内的接头。 此外，在缓冲材料层上形成TCO材料层。 此外，前接触层形成在TCO材料层上。

公开(公告)号：US20140117303A1

公开(公告)日：2014-05-01

申请号：US13722314

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

公开(公告)号：US09331279B2

公开(公告)日：2016-05-03

申请号：US14702374

申请日：2015-05-01

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E Lazovsky

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

公开(公告)号：US09331276B2

公开(公告)日：2016-05-03

申请号：US14618138

申请日：2015-02-10

Applicant: Intermolecular Inc.

Inventor： Tony P. Chiang ,  Dipankar Pramanik ,  Milind Weling

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/1253 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146

Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

公开(公告)号：US09177916B1

公开(公告)日：2015-11-03

申请号：US14553354

申请日：2014-11-25

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L23/52 ,  H01L23/528

CPC classification number: H01L27/2481 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/73 ,  H01L23/528 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are resistive switching memory cells having selectors and methods of fabricating such cells. A selector may be disposed between an electrode and resistive switching layer. The selector is configured to undergo an electrical breakdown when a voltage applied to the selector exceeds a selected threshold. The selector is formed from amorphous silicon doped with fluorine. The concentration of fluorine may be between about 0.01% atomic and 3% atomic, such as about 1% atomic. Amorphous silicon has a larger band gap than, for example, crystalline silicon and, therefore, has a lower leakage. Dangling bond and weak bond states appearing in the mid-gap position of amorphous silicon are eliminated by adding fluorine. Fluorine binds to and passivates defects. In some embodiments, a fluorine reservoir is positioned in a low current density region of the memory cell to counter diffusion of fluorine from the selector into other components.

Abstract translation: 提供了具有选择器的电阻式开关存储单元和制造这种单元的方法。 选择器可以设置在电极和电阻式开关层之间。 选择器被配置为当施加到选择器的电压超过所选择的阈值时经历电击穿。 选择器由掺杂氟的非晶硅形成。 氟的浓度可以在约0.01％原子和3％原子之间，例如约1％的原子。 无定形硅具有比例如晶体硅更大的带隙，因此具有较低的泄漏。 通过添加氟来消除出现在非晶硅中间位置的悬挂键和弱键状态。 氟结合并钝化缺陷。 在一些实施例中，氟储存器定位在存储器单元的低电流密度区域中，以防止氟从选择器到其它部件的扩散。

公开(公告)号：US20150313046A1

公开(公告)日：2015-10-29

申请号：US14259455

申请日：2014-04-23

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach

IPC: H05K9/00 ,  H01L39/24 ,  H01L39/02

CPC classification number: H01B12/02 ,  H01L39/22 ,  H01L39/24 ,  Y10S505/704 ,  Y10S505/706

Abstract: Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level. The DC voltage level may be determined by testing the superconducting circuit at different DC voltage levels and selecting the one with the lowest microwave absorption.

Abstract translation: 提供超导电路，操作这些超导电路的方法以及确定用于操作这些超导电路的处理条件的方法。 超导电路包括超导元件，导电元件和设置在超导元件和导电元件之间的介电元件。 导电元件可以是另一种超导元件，谐振元件或导电壳体。 在超导元件的操作期间，在超导元件和导电元件之间施加直流（DC）电压。 DC电压的这种应用降低了介电元件的平均微波吸收。 在一些实施例中，当首先施加DC电压时，微波吸收可以最初升高然后降低到无电压吸收水平以下。 直流电压电平可以通过在不同的直流电压电平下测试超导电路并选择具有最低微波吸收的电路来确定。

公开(公告)号：US20150262663A1

公开(公告)日：2015-09-17

申请号：US14728448

申请日：2015-06-02

Applicant: Intermolecular, Inc.

Inventor： Mankoo Lee ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: G11C13/00 ,  H01L29/78 ,  H01L29/868 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0033 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L29/785 ,  H01L29/868 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.

Abstract translation: 非线性电流响应电路可用于嵌入式电阻式存储单元，以降低功耗，同时提高存储器阵列的可靠性。 非线性电流响应电路可以包括两个背靠背泄漏的PIN二极管，两个并联的反向PIN二极管，两个背靠背的齐纳二极型金属氧化物二极管或者二极管开关元件，以及用于待机功率降低的限流电阻 低电压区域。 此外，所提出的基于1T2D1R方案的嵌入式ReRAM实现方法可以集成到先进的FEOL工艺技术中，包括用于实现高度紧凑的单元密度的立柱晶体管和/或3D鳍状场效应晶体管（FinFET）。