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    CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE
    31.
    发明申请
    CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 有权
    具有增强电容的CMOS IMAGER光电二极管

    公开(公告)号：US20120122261A1

    公开(公告)日：2012-05-17

    申请号：US13288686

    申请日：2011-11-03

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    IPC分类号： H01L31/18

    CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

    摘要： A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

    摘要翻译： 一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。 该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。 然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。 去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。 表面注入层形成在具有第一导电类型材料的沟槽的任一侧。 沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

    Self-dicing chips using through silicon vias
    32.
    发明授权
    Self-dicing chips using through silicon vias 失效
    通过硅通孔的自切割芯片

    公开(公告)号：US08168474B1

    公开(公告)日：2012-05-01

    申请号：US12987402

    申请日：2011-01-10

    申请人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Yen L. Lim

    发明人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Yen L. Lim

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L21/76898

    摘要： Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings.

    摘要翻译： 系统和方法同时在衬底中形成第一开口和第二开口。 第一开口形成为小于第二开口。 该方法还同时在第一开口和第二开口中形成第一材料。 第一材料填充第一开口，第一材料将第二开口排列。 该方法形成与第二开口中的第一材料不同的第二材料。 第二材料填充第二开口。 该方法在第二开口内的第一材料和第二材料上形成多个集成电路结构。 该方法对基板施加机械应力以使基板沿着第一开口分开。

    Pixel sensor cell with frame storage capability
    33.
    发明授权
    Pixel sensor cell with frame storage capability 有权
    具有帧存储能力的像素传感器单元

    公开(公告)号：US08009215B2

    公开(公告)日：2011-08-30

    申请号：US12174264

    申请日：2008-07-16

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

    IPC分类号： H04N3/14 ,  H04N5/335

    CPC分类号： H04N5/37452

    摘要： A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

    摘要翻译： 在CMOS图像传感器的保持栅晶体管和传输栅极晶体管之间提供一组帧传输晶体管，以便能够在曝光之后存储在感光二极管中产生的电荷。 可以在CMOS图像传感器的多次曝光之后，在每个帧转移晶体管中的每个电荷向着传输门晶体管移动之前执行来自该组帧转移晶体管的电荷的读出。 启用有用的操作模式，包括用于快速捕获连续图像的突发模式操作和其中以不同曝光时间拍摄多个图像的高动态范围操作，或者通过组合帧传输晶体管的扩散来提供大的电容。

    HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY
    34.
    发明申请
    HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY 失效
    高效CMOS图像传感器像素采用动态电压供应

    公开(公告)号：US20100097511A1

    公开(公告)日：2010-04-22

    申请号：US12641589

    申请日：2009-12-18

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

    IPC分类号： H04N5/335 ,  G06F17/50

    CPC分类号： H04N5/361 ,  G06F17/5063 ,  H04N5/359 ,  H04N5/3745

    摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

    摘要翻译： 提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。 复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。 此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

    Method of adding fabrication monitors to integrated circuit chips
    36.
    发明授权
    Method of adding fabrication monitors to integrated circuit chips 失效
    将制造监控器添加到集成电路芯片的方法

    公开(公告)号：US07620931B2

    公开(公告)日：2009-11-17

    申请号：US11859890

    申请日：2007-09-24

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

    IPC分类号： G06F17/50

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

    摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

    CMOS IMAGE SENSOR WITH REDUCED DARK CURRENT
    37.
    发明申请
    CMOS IMAGE SENSOR WITH REDUCED DARK CURRENT 有权
    CMOS图像传感器具有降低的电流

    公开(公告)号：US20090242949A1

    公开(公告)日：2009-10-01

    申请号：US12056305

    申请日：2008-03-27

    申请人： James W. Adkisson ,  Rajendran Krishnasamy

    发明人： James W. Adkisson ,  Rajendran Krishnasamy

    IPC分类号： H01L31/113 ,  H01L31/18

    CPC分类号： H01L27/14603

    摘要： A carbon-containing semiconductor layer is formed on exposed surfaces of a p-doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.

    摘要翻译： 在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。 在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。 随后形成浅沟槽隔离结构和光电二极管。 现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。 此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

    LOW LAG TRANSFER GATE DEVICE
    38.
    发明申请
    LOW LAG TRANSFER GATE DEVICE 有权
    LOW LAG传输闸门装置

    公开(公告)号：US20090180010A1

    公开(公告)日：2009-07-16

    申请号：US12013826

    申请日：2008-01-14

    申请人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan

    发明人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan

    IPC分类号： H04N3/14 ,  H01L31/18

    CPC分类号： H01L31/103 ,  H04N5/353 ,  H04N5/374 ,  H04N5/3745

    摘要： A method of forming a CMOS active pixel sensor (APS) cell structure having at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.

    摘要翻译： 一种形成具有至少一个传输栅极器件和操作方法的CMOS有源像素传感器（APS）单元结构的方法。 第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。 光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方 用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。 或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间 电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

    Method for correction of defects in lithography masks
    39.
    发明授权
    Method for correction of defects in lithography masks 失效
    光刻掩模中缺陷校正方法

    公开(公告)号：US07494748B2

    公开(公告)日：2009-02-24

    申请号：US10904308

    申请日：2004-11-03

    申请人： James W. Adkisson ,  Eric M. Coker ,  Christopher K. Magg ,  Jed H. Rankin ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Eric M. Coker ,  Christopher K. Magg ,  Jed H. Rankin ,  Anthony K. Stamper

    IPC分类号： G03F1/00

    CPC分类号： G03F1/72 ,  G03F1/70

    摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.

    摘要翻译： 用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。 原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。 形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。