公开(公告)号：US06240003B1

公开(公告)日：2001-05-29

申请号：US09562192

申请日：2000-05-01

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G11C1500

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A CAM device that utilizes a portion of a desired content as a row address is provided. A row in a CAM memory array is accessed using the row address portion of the desired content. The remaining portion of the desired content is used as a key data tag for comparison with content stored within memory locations of the addressed row. This way, the CAM device does not have to sequentially access each row in the memory array to locate memory cells having the desired content. The CAM can comprise a standard DRAM memory array, sense amplifiers and compare logic located in the sense amplifiers. Alternatively, the CAM device can comprise a standard SRAM memory array and associated compare logic. By accessing the CAM device using a portion of the desired content as a row address, the CAM device can perform a high speed search while also reducing the complexity of the CAM circuitry.

摘要翻译： 提供了将期望内容的一部分用作行地址的CAM设备。 使用所需内容的行地址部分访问CAM存储器阵列中的一行。 期望内容的剩余部分被用作用于与存储在寻址行的存储器位置内的内容进行比较的关键数据标签。 这样，CAM设备不必顺序访问存储器阵列中的每一行以定位具有期望内容的存储单元。 CAM可以包括标准DRAM存储器阵列，读出放大器和位于读出放大器中的比较逻辑。 或者，CAM设备可以包括标准SRAM存储器阵列和相关联的比较逻辑。 通过使用所需内容的一部分作为行地址访问CAM设备，CAM设备可以执行高速搜索，同时还降低CAM电路的复杂性。

公开(公告)号：US5334550A

公开(公告)日：1994-08-02

申请号：US4813

申请日：1993-01-15

申请人： David J. McElroy ,  Sung-Wei Lin ,  Manzur Gill

发明人： David J. McElroy ,  Sung-Wei Lin ,  Manzur Gill

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/28 ,  H01L21/308 ,  H01L21/74 ,  H01L21/768 ,  H01L29/423 ,  H01L21/76

CPC分类号： H01L21/76802 ,  H01L21/033 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/3081 ,  H01L21/743 ,  H01L29/78

摘要： An integrated circuit structure and process relating to a self-aligned window at the recessed junction of two insulating regions formed on the surface of a semiconductor body. The window may include a trench forming an isolation region between doped semiconductor regions, or may include an electrical conductor connected to a doped semiconductor region, or may include an electrical conductor separated from doped semiconductor regions by an electrical insulator. Embodiments include, but are not limited to, a field-effect transistor, a tunnelling area for a floating gate transistor, and an electrical connection to a doped area of the substrate.

摘要翻译： 在半导体本体的表面上形成的两个绝缘区的凹陷结的自对准窗有关的集成电路结构和工艺。 窗口可以包括在掺杂半导体区域之间形成隔离区域的沟槽，或者可以包括连接到掺杂半导体区域的电导体，或者可以包括通过电绝缘体与掺杂半导体区域分离的电导体。 实施例包括但不限于场效应晶体管，用于浮栅晶体管的隧穿区域以及与衬底的掺杂区域的电连接。

公开(公告)号：US4701885A

公开(公告)日：1987-10-20

申请号：US634899

申请日：1984-07-26

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G11C11/408 ,  G11C11/4097 ,  G11C11/40

CPC分类号： G11C11/408 ,  G11C11/4097

摘要： A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a quasi-folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of the two segments to be connected to one of the two bit lines. Instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.

公开(公告)号：US4493057A

公开(公告)日：1985-01-08

申请号：US424124

申请日：1982-09-27

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G11C11/404 ,  G11C16/04 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/115 ,  G11C11/40

CPC分类号： H01L21/768 ,  G11C11/404 ,  G11C16/0491 ,  H01L21/76216 ,  H01L23/522 ,  H01L27/115 ,  H01L2924/0002

摘要： An improved method of making a semiconductor device such as an N-channel, double level poly, MOS read only memory or ROM array is provided; the array is of very dense structure and may be electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon or metal row address lines. The electrical programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate. The very dense array results from a simplified manufacturing process generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride (functioning as an oxidation mask) are created in one mask step before field oxide is grown, then a perpendicular pattern of conductive strips is etched using a second mask step.

摘要翻译： 提供了制造诸如N沟道，双层多晶硅，仅MOS只读存储器或ROM阵列的半导体器件的改进方法; 该阵列结构非常致密，并且可以通过位于栅极氧化物和由多晶硅或金属行地址线形成的控制栅极之间的浮栅来电可编程。 通过向源极，漏极，控制栅极和衬底施加选择的电压来实现电池的电气编程。 非常密集的阵列源自通常与标准N沟道硅栅极技术兼容的简化制造工艺。 在场氧化物生长之前，在一个掩模步骤中产生栅极氧化物，多晶硅和氮化物的平行条（用作氧化掩模），然后使用第二掩模步骤蚀刻导电条的垂直图案。

公开(公告)号：US4464734A

公开(公告)日：1984-08-07

申请号：US399038

申请日：1982-07-16

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： H01L21/762 ,  H01L23/522 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L23/522 ,  H01L21/76216 ,  H01L27/10805 ,  H01L2924/0002

摘要： A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

摘要翻译： 一种晶体管类型的动态读/写存储单元是通过单级多晶硅工艺制成的，其中存取晶体管的字线和栅极由金属条形成。 不需要金属到硅或金属到多晶硅的接触。 存取晶体管通过蚀刻通过作为电容器偏置板的多晶硅条制成。 晶体管的尺寸不是由对准精度决定的。

公开(公告)号：US4443864A

公开(公告)日：1984-04-17

申请号：US310014

申请日：1981-10-13

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G06F13/42 ,  G11C8/00 ,  G06F11/00

CPC分类号： G06F13/4234 ,  G11C8/00

摘要： A memory system for a digital processor device having a 16-bit bidirectional bus with multiplexed addresses and data employs separate memory devices for the high order and low order data bytes. When less than 64K words of memory are used, there are unused address lines in the bus. A microcomputer may use memory devices partitioned 4K.times.8, needing 12 address pins. Both devices are constructed the same, but one accesses the low order byte and the other the high order byte under control of a single byte-select terminal. Mapping of the bus to memory device connections and internal connection of unused pins to address inputs or data input/output lines within the memory devices, along with the byte-select function, allow a single type of device to function in either position.

摘要翻译： 具有具有多路复用地址和数据的16位双向总线的数字处理器设备的存储器系统使用用于高阶和低阶数据字节的分开的存储器件。 当使用小于64K字的存储器时，总线中有未使用的地址线。 微型计算机可能会使用分区4Kx8的存储器件，需要12个地址引脚。 两个器件都是相同的，但是在单个字节选择端子的控制下，它们访问低位字节，另一个访问高位字节。 将总线映射到存储器件连接以及未使用引脚的内部连接到存储器件内的地址输入或数据输入/输出线以及字节选择功能允许单一类型的器件在任一位置上工作。

公开(公告)号：US4282446A

公开(公告)日：1981-08-04

申请号：US80712

申请日：1979-10-01

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G11C17/00 ,  G11C5/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H03K5/00 ,  G11C11/40 ,  H01L27/02 ,  H01L29/78

CPC分类号： G11C5/063 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/24 ,  H01L27/115 ,  H01L29/7885

摘要： A floating gate type electrically programmable memory device is made by an N-channel double-level polysilicon self-aligned process which results in a very dense array. The programming inefficiency caused by inherent resistance of elongated diffused regions used as column lines is overcome by a capacitive discharge programming method. Distributed capacitance of the column lines is charged to the programming voltage before the selected row line is brought to a high voltage, producing a pulse of current through the cell. A series of these programming pulses may be used.

摘要翻译： 通过N沟道双电平多晶硅自对准工艺制造浮栅型电可编程存储器件，其导致非常密集的阵列。 通过电容放电编程方法克服了用作列线的细扩散区域的固有电阻引起的编程效率低下。 在选择的行线达到高电压之前，将列线的分布电容充电到编程电压，产生通过电池的电流脉冲。 可以使用一系列编程脉冲。

公开(公告)号：US4219836A

公开(公告)日：1980-08-26

申请号：US907235

申请日：1978-05-18

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G11C17/12 ,  H01L23/522 ,  H01L27/112 ,  H01L29/02

CPC分类号： H01L27/112 ,  G11C17/126 ,  H01L23/522 ,  H01L2924/0002

摘要： A contact programmable, small cell area MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines are metal, gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by presence or absence of a contact engaging the polysilicon gate over the thin gate oxide.

摘要翻译： 通过与标准N沟道硅栅极制造方法兼容的工艺形成接触可编程的小单元区MOS只读存储器或ROM。 地址线是金属，门是二级多晶硅，输出和接地线由细长的N +区限定。 阵列中的每个电位MOS晶体管被编程为逻辑“1”或“0”，通过存在或不存在与多晶硅栅极接合在薄栅极氧化物上的接触。

公开(公告)号：US4184207A

公开(公告)日：1980-01-15

申请号：US923876

申请日：1978-07-12

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G11C11/404 ,  G11C16/04 ,  H01L21/033 ,  H01L21/768 ,  H01L23/525 ,  H01L27/115 ,  G11C11/40

CPC分类号： H01L27/115 ,  G11C11/404 ,  G11C16/0491 ,  H01L21/033 ,  H01L21/768 ,  H01L23/525 ,  H01L2924/0002

摘要： An N-channel double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level poly is then applied as strips overlying the original strips.

摘要翻译： N沟道双级多MOS MOS只读存储器或ROM阵列可通过浮置栅极电可编程，栅极氧化物和由多晶硅行地址线形成的控制栅极之间插入。 可以通过将选择的电压施加到源极，漏极，控制栅极和衬底来对电池进行电气编程。 通过简化的制造工艺获得非常密集的阵列，其通常与标准N沟道硅栅极技术兼容。 施加栅极氧化物，多晶硅和氮化物氧化掩模的平行条纹，生长场氧化物，然后蚀刻条纹的垂直图案，去除场氧化物以及部分原始条带，提供扩散掩模。 然后将第二级聚合物作为覆盖原始条带的条带施加。

公开(公告)号：US4139785A

公开(公告)日：1979-02-13

申请号：US801695

申请日：1977-05-31

申请人： David J. McElroy

发明人： David J. McElroy

IPC分类号： G11C11/39 ,  G11C11/412 ,  H01L21/02 ,  H01L21/3215 ,  H01L23/535 ,  H01L27/11 ,  H01L29/04 ,  H03K3/356 ,  G11C11/40 ,  H03K3/353

CPC分类号： H01L28/20 ,  G11C11/39 ,  G11C11/412 ,  H01L21/32155 ,  H01L23/535 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1112 ,  H01L29/04 ,  H03K3/356 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/904

摘要： An integrated semiconductor memory device of the static type uses a memory cell circuit having an MOS transistor of the conventional type as the access transistor, along with a resistance element buried under field oxide and an inverted field-effect transistor formed by a polycrystalline layer over a gate region. The MOS transistor connects a storage node to the access line, and the inverted field-effect transistor connects the storage node to reference potential. The storage node is connected to a second node through the resistance element, and a resistor connects the second node to a voltage supply; the magnitude of the resistance element varies according to the voltage on the storage node. The impedance of the inverted field-effect is determined by the voltage on the second node which is a moat region forming the gate.

摘要翻译： 静态的集成半导体存储器件使用具有常规类型的MOS晶体管的存储单元电路作为存取晶体管，以及埋在场氧化物之下的电阻元件和由多晶层形成的反向场效应晶体管 门区域。 MOS晶体管将存储节点连接到接入线，并且反相场效应晶体管将存储节点连接到参考电位。 存储节点通过电阻元件连接到第二节点，并且电阻器将第二节点连接到电压源; 电阻元件的大小根据存储节点上的电压而变化。 反向场效应的阻抗由作为形成栅极的护城河区域的第二节点上的电压确定。