公开(公告)号：US08816418B2

公开(公告)日：2014-08-26

申请号：US13617148

申请日：2012-09-14

申请人： Hyongsoo Kim ,  Eunkee Hong ,  Kwangtae Hwang

发明人： Hyongsoo Kim ,  Eunkee Hong ,  Kwangtae Hwang

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L29/66

CPC分类号： H01L27/108 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/66 ,  H01L29/94

摘要： A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.

摘要翻译： 一种半导体存储器件，包括在基板上的至少一个支撑图案，穿透支撑图案的存储节点，设置在存储节点和支撑图案周围的电极层，以及介于该存储节点和电极层之间的电容器电介质。 支持图案包括氧化锗。

公开(公告)号：US08748263B2

公开(公告)日：2014-06-10

申请号：US13546518

申请日：2012-07-11

申请人： Honggun Kim ,  ByeongJu Bae ,  Seung-Heon Lee ,  Mansug Kang ,  Eunkee Hong

发明人： Honggun Kim ,  ByeongJu Bae ,  Seung-Heon Lee ,  Mansug Kang ,  Eunkee Hong

IPC分类号： H01L21/8242 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76897 ,  H01L21/02164 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894

摘要： In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed.

摘要翻译： 在制造半导体器件的方法中，隔离结构形成在衬底中以限定有源区。 导电结构形成在衬底上以交叉至少两个有源区和隔离结构，导电结构沿第一方向延伸。 在与导电结构接触的衬底上共形形成界面层。 第一绝缘层设置在界面层上，其中使用可流动化学气相沉积（CVD）工艺形成第一绝缘层，并且其中界面层减小在导电结构和第一绝缘体之间的界面处产生的拉伸应力 同时形成第一绝缘层。

公开(公告)号：US20120252182A1

公开(公告)日：2012-10-04

申请号：US13369476

申请日：2012-02-09

申请人： Kyungmun BYUN ,  Byoungdeog Choi ,  Eunkee Hong ,  Mansug Kang

发明人： Kyungmun BYUN ,  Byoungdeog Choi ,  Eunkee Hong ,  Mansug Kang

IPC分类号： H01L21/8239

CPC分类号： H01L21/76229 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11531 ,  H01L29/945

摘要： A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region, forming a first trench having a first width in the first region and a second trench having a second width in the second region, and the second width is greater than the first width. The method also includes forming a first insulation layer in the first and second trenches, removing the first insulation layer in the second trench to form a first insulation pattern that includes the first insulation layer remaining in the first trench, forming on the substrate a second insulation layer that fills the second trench, and the second insulation layer includes a different material from the first insulation layer.

摘要翻译： 一种制造半导体器件的方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成具有第一宽度的第一沟槽和在第二区域中具有第二宽度的第二沟槽，第二宽度为 大于第一宽度。 该方法还包括在第一沟槽和第二沟槽中形成第一绝缘层，去除第二沟槽中的第一绝缘层以形成第一绝缘图案，其包括残留在第一沟槽中的第一绝缘层，在衬底上形成第二绝缘层 层，其填充第二沟槽，并且第二绝缘层包括与第一绝缘层不同的材料。

公开(公告)号：US20110039393A1

公开(公告)日：2011-02-17

申请号：US12856262

申请日：2010-08-13

申请人： Yongsoon Choi ,  Kyung-moon Byun ,  Eunkee Hong ,  Eun-kyung Baek

发明人： Yongsoon Choi ,  Kyung-moon Byun ,  Eunkee Hong ,  Eun-kyung Baek

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L21/31111 ,  H01L27/10817 ,  H01L27/10852

摘要： Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

摘要翻译： 提供一种制造半导体微结构的方法，该方法包括在半导体衬底上形成下部材料层，该下部材料层包括III族元素的氮化物; 在下部材料层上形成模具材料层; 在所述模具材料层上形成蚀刻掩模，所述蚀刻掩模用于在所述模具材料层中形成结构; 通过使用蚀刻掩模对模具材料层和下部材料层进行各向异性蚀刻; 并对模具材料层和下部材料层进行各向同性蚀刻。

公开(公告)号：US20060094243A1

公开(公告)日：2006-05-04

申请号：US11298785

申请日：2005-12-09

申请人： Eunkee Hong ,  Kyutae Na ,  Juseon Goo ,  Hong Kim

发明人： Eunkee Hong ,  Kyutae Na ,  Juseon Goo ,  Hong Kim

IPC分类号： H01L21/311

CPC分类号： H01L21/76837 ,  C08L83/16 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76232 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/823475 ,  H01L21/823481

摘要： Compositions that can be used in semiconductor manufacturing processes, comprising perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index of about 1.8 to about 3.0 are provided. Solutions comprising the compositions of the present invention, methods of forming films in a semiconductor manufacturing process, and methods of manufacturing semiconductor devices are also provided.

公开(公告)号：US08927389B2

公开(公告)日：2015-01-06

申请号：US13369476

申请日：2012-02-09

申请人： Kyungmun Byun ,  Byoungdeog Choi ,  Eunkee Hong ,  Mansug Kang

发明人： Kyungmun Byun ,  Byoungdeog Choi ,  Eunkee Hong ,  Mansug Kang

IPC分类号： H01L21/00 ,  H01L27/105 ,  H01L27/108 ,  H01L29/94 ,  H01L21/762 ,  H01L27/115

CPC分类号： H01L21/76229 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11531 ,  H01L29/945

摘要： A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region, forming a first trench having a first width in the first region and a second trench having a second width in the second region, and the second width is greater than the first width. The method also includes forming a first insulation layer in the first and second trenches, removing the first insulation layer in the second trench to form a first insulation pattern that includes the first insulation layer remaining in the first trench, forming on the substrate a second insulation layer that fills the second trench, and the second insulation layer includes a different material from the first insulation layer.

摘要翻译： 一种制造半导体器件的方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成具有第一宽度的第一沟槽和在第二区域中具有第二宽度的第二沟槽，第二宽度为 大于第一宽度。 该方法还包括在第一沟槽和第二沟槽中形成第一绝缘层，去除第二沟槽中的第一绝缘层以形成第一绝缘图案，其包括残留在第一沟槽中的第一绝缘层，在衬底上形成第二绝缘层 层，其填充第二沟槽，并且第二绝缘层包括与第一绝缘层不同的材料。

公开(公告)号：US20130095637A1

公开(公告)日：2013-04-18

申请号：US13586325

申请日：2012-08-15

申请人： Honggun KIM ,  Seung-Heon Lee ,  Mansug Kang ,  ByeongJu Bae ,  Eunkee Hong

发明人： Honggun KIM ,  Seung-Heon Lee ,  Mansug Kang ,  ByeongJu Bae ,  Eunkee Hong

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A method of fabricating a semiconductor device, the method including forming a mask layer on a semiconductor substrate; forming a trench in the semiconductor substrate using the mask layer as an etch mask; forming a first layer in the trench; and performing a first thermal treatment process on the first layer such that the first thermal treatment process is performed under an atmosphere that includes ozone and water vapor and transforms the first layer into a second layer.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在半导体衬底上形成掩模层; 在所述半导体衬底中使用所述掩模层作为蚀刻掩模形成沟槽; 在沟槽中形成第一层; 以及在所述第一层上进行第一热处理工艺，使得所述第一热处理工艺在包括臭氧和水蒸气的气氛下进行，并将所述第一层转化为第二层。

公开(公告)号：US20110241184A1

公开(公告)日：2011-10-06

申请号：US13019520

申请日：2011-02-02

申请人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

发明人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

IPC分类号： H01L29/00

CPC分类号： H01L23/562 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L23/5258 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/04 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.

摘要翻译： 集成电路器件包括多个堆叠电路层，所述多个电路层中的至少一个包括复合层间绝缘层，所述复合层间绝缘层包括具有不同机械强度和介电特性的横向相邻的第一和第二绝缘材料区域，以及设置的多个电路部件 在复合层间绝缘层中。 第一绝缘材料区域可以具有比第二绝缘材料区域更低的介电常数和更低的机械强度，使得例如第一绝缘材料区域可以位于信号线附近或其他电路特征处以在使用第二绝缘材料区域时降低电容 绝缘材料区域靠近容易受到局部机械应力的位置，诸如熔断器位置，外部连接接合位置或划线位置。

公开(公告)号：US08026147B2

公开(公告)日：2011-09-27

申请号：US12856262

申请日：2010-08-13

申请人： Yongsoon Choi ,  Kyung-moon Byun ,  Eunkee Hong ,  Eun-kyung Baek

发明人： Yongsoon Choi ,  Kyung-moon Byun ,  Eunkee Hong ,  Eun-kyung Baek

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L21/31111 ,  H01L27/10817 ,  H01L27/10852

摘要： Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

摘要翻译： 提供一种制造半导体微结构的方法，该方法包括在半导体衬底上形成下部材料层，该下部材料层包括III族元素的氮化物; 在下部材料层上形成模具材料层; 在所述模具材料层上形成蚀刻掩模，所述蚀刻掩模用于在所述模具材料层中形成结构; 通过使用蚀刻掩模对模具材料层和下部材料层进行各向异性蚀刻; 并对模具材料层和下部材料层进行各向同性蚀刻。

公开(公告)号：US20100248471A1

公开(公告)日：2010-09-30

申请号：US12732907

申请日：2010-03-26

申请人： Sang-Don Nam ,  Sang-Hoon Ahn ,  Eunkee Hong

发明人： Sang-Don Nam ,  Sang-Hoon Ahn ,  Eunkee Hong

IPC分类号： H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3105 ,  H01L21/31144 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.

摘要翻译： 提供一种制造半导体器件的方法，包括在第一和第二互连之间形成包括第一和第二互连的互连结构和绝缘材料，在互连上依次形成具有多个微孔的第一掩模层和第二掩模层 结构，将第二掩模层中的多个微孔彼此聚结并在第二掩模层中形成多个第一微孔，在第一掩模层中使用多个第一微孔形成多个第二微孔，并且去除绝缘 使用具有多个第二微孔的第一掩模层作为蚀刻掩模的材料，以便在第一和第二互连之间形成气隙。