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50 条记录 (耗时 0.022 秒)

    MEMORY CHAIN
    35.
    发明申请
    MEMORY CHAIN 有权
    记忆链

    公开(公告)号：US20090119464A1

    公开(公告)日：2009-05-07

    申请号：US11933445

    申请日：2007-11-01

    申请人： Kevin P. Grundy ,  Para K. Segaram

    发明人： Kevin P. Grundy ,  Para K. Segaram

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1689 ,  G06F12/06 ,  G06F13/4256 ,  G06F2212/1016

    摘要： A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

    摘要翻译： 一种具有多个存储器件和存储器控制器的存储器系统。 存储器件在链条中彼此耦合。 存储器控制器耦合到链路并且被配置为输出由链中的每个存储器件接收的存储器访问命令，并且选择要访问的两个或更多个存储器件的一组。

    Memory system having a multiplexed high-speed channel
    36.
    发明授权
    Memory system having a multiplexed high-speed channel 有权
    存储器系统具有复用的高速信道

    公开(公告)号：US07111108B2

    公开(公告)日：2006-09-19

    申请号：US10823499

    申请日：2004-04-12

    申请人： Kevin P. Grundy ,  Para K. Segaram

    发明人： Kevin P. Grundy ,  Para K. Segaram

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1684 ,  G06F13/4022

    摘要： A memory system having a memory controller, interface device and plurality of memory elements. The interface device is coupled to the memory controller via a first high-speed signal path. The plurality of memory elements are removably coupled to the interface device via respective second signal paths, each of the second signal paths having a lower signaling bandwidth than the first signaling path.

    摘要翻译： 一种具有存储器控制器，接口装置和多个存储器元件的存储器系统。 接口设备通过第一高速信号路径耦合到存储器控制器。 多个存储器元件经由相应的第二信号路径可移除地耦合到接口设备，每个第二信号路径具有比第一信令路径更低的信令带宽。

    Integrated twisted pair filter with a secure RIC function
    37.
    发明授权
    Integrated twisted pair filter with a secure RIC function 失效
    集成双绞线滤波器，具有安全的RIC功能

    公开(公告)号：US06185226B2

    公开(公告)日：2001-02-06

    申请号：US09103258

    申请日：1998-06-22

    申请人： Para K. Segaram ,  Roy T. Myers, Jr.

    发明人： Para K. Segaram ,  Roy T. Myers, Jr.

    IPC分类号： H04J308

    CPC分类号： H04L25/24 ,  H03H17/02

    摘要： A repeater interface controller (“RIC”) integrated circuit with integrated filters and buffer drivers is provided for use in a repeater. In one embodiment, the RIC uses two filters to filter link pulse signals and data signals for a plurality of ports. Thus, the RIC is able to concurrently provide filtered link pulses to some ports and filtered data signals to other ports. Further, because only two filters are used, the area required to implement the plurality of ports is reduced relative to conventional repeaters that use a filter for each port. In another embodiment of the present invention, a RIC includes a logic circuit and a plurality of analog multiplexers and twisted pair buffer drivers. The analog multiplexers receive signals on their input lines and select which of these signals are passed to the buffer drivers to be outputted. The logic circuit provides control signals to the analog multiplexers such that the analog multiplexers select a new input line when the signal on the new input line is approximately the same as the signal on the currently selected input line. As a result, the signal passed on to the buffer drivers remains approximately the same, thereby reducing switching noise.

    摘要翻译： 具有集成滤波器和缓冲驱动器的中继器接口控制器（“RIC”）集成电路可用于中继器。 在一个实施例中，RIC使用两个滤波器来滤波多个端口的链路脉冲信号和数据信号。 因此，RIC能够同时向某些端口提供滤波的链路脉冲，并将滤波的数据信号同时提供给其他端口。 此外，由于仅使用两个滤波器，相对于使用每个端口的滤波器的常规中继器，实现多个端口所需的面积减小。 在本发明的另一实施例中，RIC包括逻辑电路和多个模拟多路复用器和双绞线缓冲器驱动器。 模拟多路复用器在其输入线路上接收信号，并选择这些信号中的哪一个传送到缓冲器驱动器以输出。 逻辑电路向模拟多路复用器提供控制信号，使得当新输入线上的信号与当前选择的输入线上的信号大致相同时，模拟多路复用器选择新的输入线。 结果，传递到缓冲器驱动器的信号保持大致相同，从而降低开关噪声。

    Integrated waveshaping circuit using weighted current summing
    38.
    发明授权
    Integrated waveshaping circuit using weighted current summing 失效
    集成波形电路采用加权电流求和

    公开(公告)号：US5357145A

    公开(公告)日：1994-10-18

    申请号：US994660

    申请日：1992-12-22

    申请人： Para K. Segaram

    发明人： Para K. Segaram

    IPC分类号： H03M1/74 ,  H04L25/02 ,  H04L25/03 ,  H04L25/04 ,  H03K5/01

    CPC分类号： H04L25/0286 ,  H03M1/745 ,  H04L25/03853 ,  H04L25/0272 ,  H04L25/0282

    摘要： A waveshaping circuit, which includes a phase-lock-loop stage, an input logic stage, a delayed input logic stage, and a weighted current sum stage, shapes and filters a data signal to be transmitted onto the twisted-pair media of a local area network. The phase-lock-loop stage generates a series of incrementally-delayed timing signals in response to an oscillator signal. The input logic stage generates a plurality of pairs of logic signals by periodically latching a logic state and an inverse logic state of the data signal in response to the incrementally-delayed timing signals. The delayed input logic stage generates a plurality of pairs of delayed logic signals by periodically latching a logic state and an inverse logic state of an inverse data signal in response to the incrementally-delayed timing signals. The weighted current sum stage incrementally generates both an output data signal and a complementary output data signal in response to both the plurality of logic signals and the plurality of delayed logic signals.

    摘要翻译： 包括锁相环，输入逻辑级，延迟输入逻辑级和加权电流和级的波形形成电路对要发送到本地的双绞线介质上的数据信号进行形状和滤波 区域网络。 相位锁定阶段响应于振荡器信号产生一系列增量延迟的定时信号。 输入逻辑级通过响应于递增延迟的定时信号周期性地锁存数据信号的逻辑状态和反逻辑状态来产生多对逻辑信号。 响应于递增延迟的定时信号，延迟输入逻辑级通过周期性地锁存逻辑状态和逆数据信号的反逻辑状态来产生多对延迟逻辑信号。 所述加权电流和级响应于所述多个逻辑信号和所述多个延迟逻辑信号而递增地产生输出数据信号和互补输出数据信号。

    MEMORY CHAIN
    39.
    发明申请
    MEMORY CHAIN 有权
    记忆链

    公开(公告)号：US20110252164A1

    公开(公告)日：2011-10-13

    申请号：US13165206

    申请日：2011-06-21

    申请人： Kevin P. Grundy ,  Para K. Segaram

    发明人： Kevin P. Grundy ,  Para K. Segaram

    IPC分类号： G06F3/00

    CPC分类号： G06F13/1689 ,  G06F12/06 ,  G06F13/4256 ,  G06F2212/1016

    摘要： A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

    摘要翻译： 一种具有多个存储器件和存储器控制器的存储器系统。 存储器件在链条中彼此耦合。 存储器控制器耦合到链路并且被配置为输出由链中的每个存储器件接收的存储器访问命令，并且选择要访问的两个或更多个存储器件的一组。

    High-speed communication system with a feedback synchronization loop
    40.
    发明授权
    High-speed communication system with a feedback synchronization loop 失效
    具有反馈同步回路的高速通信系统

    公开(公告)号：US07593470B2

    公开(公告)日：2009-09-22

    申请号：US12174128

    申请日：2008-07-16

    申请人： Para K. Segaram

    发明人： Para K. Segaram

    IPC分类号： H04B3/00 ,  H04L25/00

    CPC分类号： H04L25/028 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/14

    摘要： In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

    摘要翻译： 在具有连接到物理层设备的物理层设备和处理设备的通信设备中，在千兆比特范围内的设备之间进行通信所需的输入/输出（I / O）端口的数量通过利用毫伏差分I / O驱动程序和接收器。 此外，校准反馈环路在处理设备上同步数据和时钟信号，从而消除了在处理设备上恢复时钟的需要。