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公开(公告)号：US06452110B1
公开(公告)日：2002-09-17
申请号：US09897889
申请日：2001-07-05
IPC分类号： H05K109
CPC分类号： H05K3/02 , H01L21/288 , H01L21/32134 , H01L21/76885 , Y10T29/49155 , Y10T29/49156
摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.
摘要翻译： 一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。 景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。 使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。 接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。 包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。
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32.发明授权Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate 失效在混合体和绝缘体上硅（SOI））衬底上制造互补金属氧化物半导体（CMOS）器件的方法公开(公告)号：US06214653B1
公开(公告)日：2001-04-10
申请号：US09325732
申请日：1999-06-04
申请人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
发明人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02675 , H01L21/02689 , H01L21/2022 , H01L21/76283 , H01L21/84
摘要： A method of forming a semiconductor substrate (and the resulting structure), includes etching a groove into a bulk silicon substrate, forming a dielectric in the groove and planarizing the silicon substrate to form at least one patterned dielectric island in the silicon substrate, forming an amorphous silicon (or SiGe) layer on exposed portions of the silicon substrate and the at least one dielectric island, crystallizing the amorphous silicon (or SiGe) layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon (or SiGe) layer to crystallized silicon, and performing a shallow trench isolation (STI) process, to form oxide isolations between devices.
摘要翻译： 一种形成半导体衬底的方法（以及所得到的结构）包括将槽蚀刻到体硅衬底中，在沟槽中形成电介质并平坦化硅衬底，以在硅衬底中形成至少一个图案化的电介质岛，形成 在硅衬底和至少一个电介质岛的暴露部分上的非晶硅（或SiGe）层，使用暴露的硅衬底作为晶种使非晶硅（或SiGe）层结晶，硅衬底与所形成的硅直接接触 作为用于晶化过程的晶体生长晶种，并且将硅（或SiGe）层转化为结晶硅，并进行浅沟槽隔离（STI）工艺，以在器件之间形成氧化物隔离。
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公开(公告)号：US07778351B2
公开(公告)日：2010-08-17
申请号：US10118750
申请日：2002-04-09
申请人： Louis L. Hsu , Li-Kong Wang , Philip J. Murfet
发明人： Louis L. Hsu , Li-Kong Wang , Philip J. Murfet
CPC分类号： H03K19/00384
摘要： A CMOS receiver system having a tunable receiver having a tunable gain and a bandwidth system is provided. The tunable receiver includes means for receiving input signals; and a control circuit controlled by a control signal for tuning at least one of the gain and the bandwidth of the tunable receiver, wherein the control signal is indicative of a data rate of the input signals. Furthermore, a method is provided for tuning a CMOS receiver receiving input signals. The method includes the steps of receiving at least one control signal, and controlling one of gain and bandwidth of the CMOS receiver in accordance with the at least one control signal, wherein the at least one control signal is indicative of a data rate of the received input signals.
摘要翻译： 提供具有可调谐增益和带宽系统的可调谐接收机的CMOS接收机系统。 可调谐接收机包括用于接收输入信号的装置; 以及由控制信号控制的控制电路，用于调谐可调接收机的增益和带宽中的至少一个，其中控制信号表示输入信号的数据速率。 此外，提供了一种用于调谐接收输入信号的CMOS接收器的方法。 该方法包括以下步骤：接收至少一个控制信号，并根据至少一个控制信号控制CMOS接收机的增益和带宽中的一个，其中至少一个控制信号指示接收的数据速率 输入信号。
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公开(公告)号：US20080171418A1
公开(公告)日：2008-07-17
申请号：US12054545
申请日：2008-03-25
IPC分类号： H01L21/02
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.
摘要翻译： 集成电路芯片的方法和结构具有包括多个绝缘和导电水平的逻辑芯，外部导体水平和具有直接连接到外部导体水平的导电聚合物的无源器件。 无源器件包含还包括电阻器，电容器和/或电感器的RF器件。 电阻器可以是蛇形电阻器，电容器可以是交错电容器。
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公开(公告)号：US07216284B2
公开(公告)日：2007-05-08
申请号：US10145018
申请日：2002-05-15
申请人： Louis L. Hsu , Brian L. Ji , Li-Kong Wang
发明人： Louis L. Hsu , Brian L. Ji , Li-Kong Wang
IPC分类号： G11C29/00
CPC分类号： G11C15/04 , G11C15/043
摘要： A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.
摘要翻译： 内容可寻址存储器（CAM）。 CAM阵列的数据部分包括字数据存储。 每个字线包括数据部分中的CAM单元（动态或静态）和公共字匹配线。 CAM阵列的纠错（例如，奇偶校验）部分包含每个字线的纠错单元。 每个字线处的误差校正单元连接到纠错匹配线。 纠错匹配线上的匹配可以对相应的数据匹配线进行预充电。 在数据比较中仅包括在纠错匹配行上具有对应匹配的字线上的数据。 预充电功率只需要一个分数（与所使用的误差校正的位长度成反比成正比）的整数组。
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公开(公告)号：US07088074B2
公开(公告)日：2006-08-08
申请号：US10039541
申请日：2002-01-02
IPC分类号： H02J7/00
CPC分类号： H01M10/425 , H01L23/58 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15153 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01M2/1066 , H01M2/204 , H01L2924/00014 , H01L2924/00
摘要： A system level device for battery and integrated circuit chip integration comprises at least one battery; at least one integrated circuit chip powered by the at least one battery; and a package connected to any of the at least one battery and the at least one integrated circuit chip, wherein the at least one battery connects to a pair of opposed upright ends of the package, wherein the at least one integrated circuit chip is disposed between the at least one battery and the package, and wherein the at least one integrated circuit chip lays on top of a portion of the package.
摘要翻译： 用于电池和集成电路芯片集成的系统级装置包括至少一个电池; 由所述至少一个电池供电的至少一个集成电路芯片; 以及连接到所述至少一个电池和所述至少一个集成电路芯片中的任一个的封装，其中所述至少一个电池连接到所述封装的一对相对的直立端，其中所述至少一个集成电路芯片设置在 所述至少一个电池和所述封装，并且其中所述至少一个集成电路芯片放置在所述封装的一部分的顶部上。
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37.发明授权Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof 失效自对准的平面化薄膜晶体管，采用该晶体管的器件及其制造方法公开(公告)号：US06818487B2
公开(公告)日：2004-11-16
申请号：US10631533
申请日：2003-07-31
IPC分类号： H01L2100
CPC分类号： H01L29/66787 , H01L27/11 , H01L27/1108 , H01L29/42384 , H01L29/66765 , H01L29/78636
摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
摘要翻译： 提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。 半导体器件具有第一场效应晶体管和第二场效应晶体管。 第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。 第二场效应晶体管包括在第一场效应晶体管上方的平坦化半导体材料层中与共享栅极自对准的源极和漏极。 在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。
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公开(公告)号：US06768063B2
公开(公告)日：2004-07-27
申请号：US09943827
申请日：2001-08-31
IPC分类号： H05K111
CPC分类号： H05K3/24 , G01N27/226 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of conductive electrodes. The electrodes are self-aligning such that the patterning manufacturing process is insensitive to variations in the positional placement of the pattern on the substrate. Moreover, a single lithographic masking layer is used for forming the pair of electrodes, which are electrically isolated. Finally, the first electrode is offset from the second electrode by a chemical surface modification of the first electrode, and an anisotropic deposition of the second electrode which is shadowed by the first electrode.
摘要翻译： 一种电极装置的方法和结构，由此第二电极沉积在第一电极上，使得一对导电电极之间的电容耦合增加。 电极是自对准的，使得图案化制造工艺对图案在衬底上的位置放置的变化不敏感。 此外，单个光刻掩模层用于形成电隔离的一对电极。 最后，第一电极通过第一电极的化学表面改性和由第一电极遮蔽的第二电极的各向异性沉积而偏离第二电极。
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公开(公告)号：US06737907B2
公开(公告)日：2004-05-18
申请号：US09898328
申请日：2001-07-03
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2001/0012 , H02M2001/0025
摘要： A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.
摘要翻译： 一种具有用于控制电压发生器系统的控制电路的编程电路的数字可编程直流电压发生器系统。 编程电路接收输入控制信号，处理输入控制信号，并将输出控制信号产生到电压发生器系统的控制电路，用于根据输入控制信号控制控制电路。 控制电路包括限幅电路和振荡电路。 输出控制信号控制至少一个限制电路，用于在达到目标输出电压时使振荡器电路无效，以及用于控制振荡器电路的泵送速度的振荡器电路。
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40.发明授权公开(公告)号：US06649935B2
公开(公告)日：2003-11-18
申请号：US09795535
申请日：2001-02-28
IPC分类号： H01L2976
CPC分类号： H01L29/66787 , H01L27/11 , H01L27/1108 , H01L29/42384 , H01L29/66765 , H01L29/78636
摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
摘要翻译： 提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。 半导体器件具有第一场效应晶体管和第二场效应晶体管。 第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。 第二场效应晶体管包括在第一场效应晶体管之上的平坦化半导体材料层中与共享栅极自对准的源极和漏极。 在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。
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