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公开(公告)号：US09892780B1
公开(公告)日：2018-02-13
申请号：US15729345
申请日：2017-10-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Hiromasa Takeda , Hiroki Fujisawa
IPC: G11C7/10 , G11C11/4093 , G11C11/4094 , G11C11/4074
CPC classification number: G11C11/4093 , G11C7/04 , G11C7/1051 , G11C7/1057 , G11C11/4074 , G11C11/4094 , G11C29/022 , G11C29/028 , G11C2207/2254
Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.
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公开(公告)号：US09865317B2
公开(公告)日：2018-01-09
申请号：US15139102
申请日：2016-04-26
Applicant: Micron Technology, Inc.
Inventor： Shuichi Ishibashi , Kazutaka Miyano , Hiroki Fujisawa
IPC: G11C7/22 , G11C7/10 , G11C11/4076 , G11C8/18 , G11C8/10
CPC classification number: G11C8/18 , G11C7/1015 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/10 , G11C11/4076 , G11C29/023 , G11C29/024 , G11C29/028 , G11C2207/2254 , G11C2207/2272
Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.
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33.发明授权公开(公告)号：US09704561B2
公开(公告)日：2017-07-11
申请号：US15393149
申请日：2016-12-28
Applicant: Micron Technology, Inc.
Inventor： Hiroki Fujisawa
IPC: G11C11/4076 , G11C11/4093 , G11C11/4091 , G11C11/4096 , G11C11/408
CPC classification number: G11C11/4076 , G11C7/1048 , G11C7/1069 , G11C11/4087 , G11C11/4091 , G11C11/4093 , G11C11/4096
Abstract: A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.
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公开(公告)号：US09627013B2
公开(公告)日：2017-04-18
申请号：US14622520
申请日：2015-02-13
Applicant: Micron Technology, Inc.
Inventor： Hiromasa Takeda , Hiroki Fujisawa
CPC classification number: G11C11/4093 , G11C7/04 , G11C7/1051 , G11C7/1057 , G11C11/4074 , G11C11/4094 , G11C29/022 , G11C29/028 , G11C2207/2254
Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.
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公开(公告)号：US20150029776A1
公开(公告)日：2015-01-29
申请号：US14336984
申请日：2014-07-21
Applicant: Micron Technology, Inc.
Inventor： Hiroki Fujisawa
IPC: H01L23/525 , G11C17/16
CPC classification number: H01L23/5252 , G11C17/16 , G11C29/789 , H01L23/5286 , H01L2924/0002 , H01L2924/00
Abstract: A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.
Abstract translation: 一种设备包括：第一电源线，用于提供第一电压，第一，第二和第三节点，连接在第一电源线和第一节点之间的选择电路，连接在第一节点和第二节点之间的第一反熔丝 以及连接在第一节点和第三节点之间的第二反熔丝。 第二节点和第三节点没有彼此连接。
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Patent Agency Ranking
公开(公告)号：US20240290376A1
公开(公告)日：2024-08-29
申请号：US18506202
申请日：2023-11-10
Applicant: Micron Technology, Inc.
Inventor： Wenlun Zhang , Hiroki Fujisawa , Shinichi Miyatake , Yuan He
IPC: G11C11/4091 , G11C5/14 , G11C11/4096
CPC classification number: G11C11/4091 , G11C5/147 , G11C11/4096
Abstract: Sense amplifiers for memory devices may include threshold voltage compensation circuitry configured to compensate a threshold voltage offset of a portion of the sense amplifier. Additionally, the sense amplifiers also perform pre-sensing of the portion of the sense amplifier. Moreover, the sense amplifier is configured to perform main sensing and latching in a phase after pre-sensing the portion of the sense amplifier.
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公开(公告)号：US20210143142A1
公开(公告)日：2021-05-13
申请号：US17125651
申请日：2020-12-17
Applicant: Micron Technology, Inc.
Inventor： Hiroki Fujisawa , Charles L. Ingalls , Richard J. Hill , Gurtej S. Sandhu , Scott J. Derner
IPC: H01L25/18 , G11C11/408 , H01L27/108 , G11C11/4091 , H01L23/528
Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
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公开(公告)号：US10957681B1
公开(公告)日：2021-03-23
申请号：US16553448
申请日：2019-08-28
Applicant: Micron Technology, Inc.
Inventor： Hiroki Fujisawa , Charles L. Ingalls , Richard J. Hill , Gurtej S. Sandhu , Scott J. Derner
IPC: G11C11/40 , H01L25/18 , G11C11/4091 , H01L23/528 , H01L27/108 , G11C11/408 , H01L29/78
Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
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公开(公告)号：US10957413B2
公开(公告)日：2021-03-23
申请号：US16176952
申请日：2018-10-31
Applicant: Micron Technology, Inc.
Inventor： Susumu Takahashi , Hiroki Fujisawa
Abstract: Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.
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公开(公告)号：US10755758B2
公开(公告)日：2020-08-25
申请号：US16107909
申请日：2018-08-21
Applicant: Micron Technology, Inc.
Inventor： Shuichi Ishibashi , Kazutaka Miyano , Hiroki Fujisawa
Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.
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