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    THREE-DIMENSIONAL BONDING SCHEME AND ASSOCIATED SYSTEMS AND METHODS
    33.
    发明申请
    THREE-DIMENSIONAL BONDING SCHEME AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20230069476A1

    公开(公告)日：2023-03-02

    申请号：US17592065

    申请日：2022-02-03

    Applicant: Micron Technology, Inc.

    Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

    OVERLAPPING DIE STACKS FOR NAND PACKAGE ARCHITECTURE
    35.
    发明申请
    OVERLAPPING DIE STACKS FOR NAND PACKAGE ARCHITECTURE 有权

    公开(公告)号：US20220068877A1

    公开(公告)日：2022-03-03

    申请号：US17003789

    申请日：2020-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Enyong Tai ,  Hem P. Takiar ,  Li Wang ,  Hong Wan Ng

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

    Abstract: A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

    Stacked semiconductor die assemblies with support members and associated systems and methods
    36.
    发明授权
    Stacked semiconductor die assemblies with support members and associated systems and methods 有权

    公开(公告)号：US11101262B2

    公开(公告)日：2021-08-24

    申请号：US16678195

    申请日：2019-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Hong Wan Ng ,  Seng Kim Ye

    IPC: H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

    Through stack bridge bonding devices and associated methods
    39.
    发明授权
    Through stack bridge bonding devices and associated methods 有权

    公开(公告)号：US12237301B2

    公开(公告)日：2025-02-25

    申请号：US17750225

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

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