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    VOID FORMATION IN CHARGE TRAP STRUCTURES
    31.
    发明申请
    VOID FORMATION IN CHARGE TRAP STRUCTURES 审中-公开

    公开(公告)号：US20200020703A1

    公开(公告)日：2020-01-16

    申请号：US16580751

    申请日：2019-09-24

    Applicant: Micron Technology, Inc.

    Inventor： Chris M. Carlson ,  Ugo Russo

    IPC: H01L27/1157 ,  H01L29/51 ,  H01L29/423 ,  H01L27/11582 ,  H01L21/28

    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

    METHODS OF OPERATING MEMORY DEVICES AND ELECTRONIC SYSTEMS
    32.
    发明申请
    METHODS OF OPERATING MEMORY DEVICES AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20190081104A1

    公开(公告)日：2019-03-14

    申请号：US16185729

    申请日：2018-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Andrea Redaelli ,  Giorgio Servalli

    IPC: H01L27/24 ,  H01L45/00

    Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.

    VOID FORMATION IN CHARGE TRAP STRUCTURES
    33.
    发明申请
    VOID FORMATION IN CHARGE TRAP STRUCTURES 审中-公开

    公开(公告)号：US20190051656A1

    公开(公告)日：2019-02-14

    申请号：US15675265

    申请日：2017-08-11

    Applicant: Micron Technology, Inc.

    Inventor： Chris M. Carlson ,  Ugo Russo

    IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28

    CPC classification number: H01L27/1157 ,  H01L27/11582 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513

    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

    Memory cells, integrated devices, and methods of forming memory cells
    36.
    发明授权
    Memory cells, integrated devices, and methods of forming memory cells 有权
    存储单元，集成器件和形成存储单元的方法

    公开(公告)号：US09570677B2

    公开(公告)日：2017-02-14

    申请号：US15049100

    申请日：2016-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Ugo Russo ,  Agostino Pirovano ,  Simone Lavizzari

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

    Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.

    Abstract translation: 一些实施例包括集成设备，诸如存储器单元。 这些装置可以包括硫族化物材料，在硫族化物材料上的导电材料，以及在导电材料和硫族化物材料之间的散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。 一些实施例包括形成存储器单元的方法。 可以在加热器材料上形成硫族化物材料。 可以在硫族化物材料上形成导电材料。 可以在导电材料和硫族化物材料之间形成散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。

    TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE
    37.
    发明申请
    TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE 有权

    公开(公告)号：US20250157549A1

    公开(公告)日：2025-05-15

    申请号：US19022744

    申请日：2025-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Karan Banerjee ,  Shyam Sunder Raghunathan

    IPC: G11C16/26

    Abstract: A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.

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