公开(公告)号：US20210193843A1

公开(公告)日：2021-06-24

申请号：US16723259

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Shen Hu ,  Hung-Wei Liu ,  Xiao Li ,  Zhiqiang Xie ,  Corey Staller ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Thomas A. Figura

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An example apparatus includes forming a working surface of a substrate material. The example apparatus includes trench formed between two semiconductor structures on the working surface of the substrate material. The example apparatus further includes access lines formed on neighboring sidewalls of the semiconductor structures opposing a channel region separating a first source/drain region and a second source/drain region. The example apparatus further includes a time-control formed inhibitor material formed over a portion of the sidewalls of the semiconductor structures. The example apparatus further includes a dielectric material formed over the semiconductor structures to enclose a non-solid space between the access lines.

公开(公告)号：US10541229B2

公开(公告)日：2020-01-21

申请号：US14626575

申请日：2015-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Anilkumar Chandolu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/367

Abstract: Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

公开(公告)号：US20190341325A1

公开(公告)日：2019-11-07

申请号：US16431988

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： James M. Derderian ,  Andrew M. Bayless ,  Xiao Li

IPC: H01L23/367 ,  H01L23/532 ,  H01L23/498

Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.

公开(公告)号：US10431519B1

公开(公告)日：2019-10-01

申请号：US15969978

申请日：2018-05-03

Applicant: Micron Technology, Inc.

Inventor： James M. Derderian ,  Andrew M. Bayless ,  Xiao Li

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/532 ,  H01L23/498 ,  B32B43/00 ,  B32B7/12

Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.

公开(公告)号：US20190122950A1

公开(公告)日：2019-04-25

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10163755B2

公开(公告)日：2018-12-25

申请号：US15498321

申请日：2017-04-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L21/52 ,  H01L21/54 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/44 ,  H01L25/00 ,  H01L25/18 ,  H01L23/053 ,  H01L23/367 ,  H01L23/373

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20170229439A1

公开(公告)日：2017-08-10

申请号：US15498321

申请日：2017-04-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00 ,  H01L23/44 ,  H01L25/18 ,  H01L23/367

CPC classification number: H01L23/44 ,  H01L21/50 ,  H01L21/52 ,  H01L21/54 ,  H01L21/563 ,  H01L23/04 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3736 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20250056802A1

公开(公告)日：2025-02-13

申请号：US18930589

申请日：2024-10-29

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

公开(公告)号：US12167604B2

公开(公告)日：2024-12-10

申请号：US18381791

申请日：2023-10-19

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

公开(公告)号：US11969140B2

公开(公告)日：2024-04-30

申请号：US17354179

申请日：2021-06-22

Applicant: Micron Technology, Inc.

Inventor： Priya Vemparala Guruswamy ,  Chunhua Yao ,  Anshika Sharma ,  Xiao Li ,  Cipriana Forgy

IPC: A47L9/28 ,  A47L11/28 ,  A47L11/40 ,  B08B1/04 ,  B08B3/08 ,  B08B5/04 ,  G06N20/00

CPC classification number: A47L9/2826 ,  A47L9/2847 ,  A47L9/2894 ,  A47L11/28 ,  A47L11/408 ,  B08B1/04 ,  B08B3/08 ,  B08B5/04 ,  A47L2201/04 ,  A47L2201/06 ,  G06N20/00

Abstract: Methods and apparatuses associated with surface cleaning are described. Examples can include detecting at a processing resource of a robot and via a temperature sensor of the robot, a temperature of a surface on which the robot is located. Examples can include the processing resource shutting down the robot in response to the temperature being at or above a particular threshold temperature, and the processing resource instructing the robot to clean the surface following a particular cleaning path using a vacuum, a scrubber, or both in response to the temperature being below a particular threshold temperature.