公开(公告)号：US20080258198A1

公开(公告)日：2008-10-23

申请号：US12166690

申请日：2008-07-02

申请人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L29/76

CPC分类号： H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising: a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

摘要翻译： 本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。 本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。 具体地说，本发明提供了一种金属叠层，包括：铪基电介质; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。

公开(公告)号：US20080249650A1

公开(公告)日：2008-10-09

申请号：US11696507

申请日：2007-04-04

申请人： Russell D. Allen ,  Stephen L. Brown ,  Alessandro C. Callegari ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Russell D. Allen ,  Stephen L. Brown ,  Alessandro C. Callegari ,  Michael P. Chudzik ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： G06F19/00 ,  G01N21/00

CPC分类号： G01N21/8422 ,  G01N21/59 ,  H01L22/12 ,  H01L22/20

摘要： Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.

摘要翻译： 使用消光系数k的测量来有效且迅速地在线监测和/或控制金属膜组合物。 消光系数对金属化合物的组成的依赖性的特征在于测量一系列具有不同组成的金属化合物的消光系数。 然后将监测金属膜沉积在晶片上。 测量晶片上的膜的消光系数k并提取膜组成参数。 如果k在规范中，则可以继续进行晶片处理，或者可以从k的测量值中提取所需的胶片组成变化，并且建立k的关于对于超出规格k值的胶片的组成的依赖性。

公开(公告)号：US20080203485A1

公开(公告)日：2008-08-28

申请号：US11680108

申请日：2007-02-28

申请人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

发明人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

摘要翻译： 用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。 第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：US06770526B2

公开(公告)日：2004-08-03

申请号：US10294100

申请日：2002-11-14

申请人： Michael P. Chudzik ,  Jochen Beintner ,  Joseph F. Shepard, Jr.

发明人： Michael P. Chudzik ,  Jochen Beintner ,  Joseph F. Shepard, Jr.

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L27/10817 ,  H01L29/66181 ,  H01L29/945

摘要： A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

公开(公告)号：US06653246B2

公开(公告)日：2003-11-25

申请号：US10338481

申请日：2003-01-08

申请人： Michael P. Chudzik ,  Lawrence Clevenger ,  Louis L. Hsu ,  Deborah A. Neumayer ,  Joseph F. Shepard, Jr.

发明人： Michael P. Chudzik ,  Lawrence Clevenger ,  Louis L. Hsu ,  Deborah A. Neumayer ,  Joseph F. Shepard, Jr.

IPC分类号： H01L2131

CPC分类号： C23C16/45525 ,  C23C16/40 ,  C23C16/56 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31604 ,  H01L21/3162

摘要： A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor deposition of La2O3 and Al2O3 using ratios between 20%-50% La2O3 and 50%-80%

摘要翻译： 一种用于集成电路结构的方法和结构，其包括在衬底上引入前体，氧化前体并加热前体。 前体的引入和氧化以使得在衬底上形成无定形玻璃电介质的方式进行。 在将前体引入基片之前，该方法优选地包括清洁基底。 前体的引入以与玻璃膜的形成一致的摩尔比进行，并且可以包括使用20％-50％La 2 O 3和50％-80％之间的比率的La 2 O 3和Al 2 O 3的原子级化学气相沉积

公开(公告)号：US09318336B2

公开(公告)日：2016-04-19

申请号：US13326767

申请日：2011-12-15

申请人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

发明人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49

CPC分类号： H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

公开(公告)号：US08759172B2

公开(公告)日：2014-06-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US20140001575A1

公开(公告)日：2014-01-02

申请号：US13534012

申请日：2012-06-27

申请人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

发明人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

摘要翻译： 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

公开(公告)号：US20130277764A1

公开(公告)日：2013-10-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US08518766B2

公开(公告)日：2013-08-27

申请号：US13536366

申请日：2012-06-28

申请人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Vijay Narayanan ,  Martin P. O'Boyle ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Vijay Narayanan ,  Martin P. O'Boyle ,  Vamsi K. Paruchuri

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/70

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/51

摘要： A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.

摘要翻译： 场效应晶体管（FET）包括至少部分地设置在身体区域中的体区和源区。 FET还包括至少部分地设置在体区中的漏极区域和氮氧化钼（MoNO）栅极。 FET还包括具有高介电常数（k）的电介质，其布置在体区和MoNO门之间。