公开(公告)号：US10978478B1

公开(公告)日：2021-04-13

申请号：US16716947

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: G11C8/10 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/08 ,  G11C11/56 ,  H01L21/768 ,  H01L21/3213 ,  G11C16/24

Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

公开(公告)号：US10714166B2

公开(公告)日：2020-07-14

申请号：US16101600

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: G11C8/08 ,  G11C11/408 ,  G11C7/10 ,  G11C16/08 ,  G11C7/12 ,  G11C8/12 ,  G11C16/04 ,  G11C8/10

Abstract: Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, each driver circuitry connected to a respective block of memory cells, as well as methods of operating such memories.

公开(公告)号：US10248500B2

公开(公告)日：2019-04-02

申请号：US15267844

申请日：2016-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Mark A. Helm ,  Aaron S. Yip

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/52 ,  H03M13/11 ,  H03M13/37 ,  H03M13/00 ,  G11C29/04 ,  H03M13/29

Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.

公开(公告)号：US20170330627A1

公开(公告)日：2017-11-16

申请号：US15665474

申请日：2017-08-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/26

Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to selected memory cells of a programming operation, assigning the selected memory cells to respective groups of memory cells each having a different range of threshold voltages, determining a respective value of VgVt for each group of memory cells, applying a subsequent programming pulse to the selected access line and having a particular voltage level determined in response to the value of VgVt for a particular group of memory cells, enabling the selected memory cells of the particular group of memory cells for programming while the subsequent programming pulse has the particular voltage level, and repeating for a next group of memory cells.

公开(公告)号：US20170271014A1

公开(公告)日：2017-09-21

申请号：US15072954

申请日：2016-03-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/26

Abstract: Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of groups of memory cells to a particular range of threshold voltages, applying a stepped programming pulse to a selected access line connected to each memory cell of the plurality of groups of memory cells, and enabling each group of memory cells for programming when a voltage level of the stepped programming pulse corresponds to the respective indication of the programming voltage sufficient to program that group of memory cells to the particular range of threshold voltages.

公开(公告)号：US09514829B2

公开(公告)日：2016-12-06

申请号：US14958217

申请日：2015-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

IPC: G11C5/14 ,  G11C16/24 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

公开(公告)号：US11915758B2

公开(公告)日：2024-02-27

申请号：US18095049

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

公开(公告)号：US11688463B2

公开(公告)日：2023-06-27

申请号：US16948236

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Tomoko Ogura Iwasaki

IPC: H01L29/04 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L29/04

Abstract: A memory device comprises a substrate and a memory array disposed above the substrate, the memory array comprising a plurality of vertically stacked layers, each vertically stacked layer comprising a plurality of word lines. The memory device further comprises a plurality of vertical string driver circuits disposed above the memory array, wherein each of the plurality of vertical string driver circuits comprises one or more semiconductor devices coupled to a respective one of the plurality of word lines.

公开(公告)号：US11636886B2

公开(公告)日：2023-04-25

申请号：US17392924

申请日：2021-08-03

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Theodore T. Pekny

IPC: G11C16/26 ,  G11C8/08 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

公开(公告)号：US20230059543A1

公开(公告)日：2023-02-23

申请号：US17887940

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

IPC: G06F3/06

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.