公开(公告)号：US06313037B1

公开(公告)日：2001-11-06

申请号：US09576255

申请日：2000-05-24

申请人： Akihiro Kajita ,  Noriaki Matsunaga ,  Kazuyuki Higashi

发明人： Akihiro Kajita ,  Noriaki Matsunaga ,  Kazuyuki Higashi

IPC分类号： H01L2144

CPC分类号： H01L23/485 ,  H01L21/76807 ,  H01L21/76885 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor comprising a semiconductor device formed on a semiconductor substrate, an interlevel insulating film having holes and a ring-shaped groove in a circuit area formed on the semiconductor substrate and having the semiconductor element formed therein, the ring-shaped groove seamlessly surrounding an outer periphery of the circuit area, via plugs formed in the holes in the interlevel insulating film, a wiring connected to the plug electrodes and mainly comprising copper, and a via ring having a layer formed in the ring-shaped groove and mainly comprising aluminum, wherein no layer mainly comprising copper is formed in the via ring layer.

公开(公告)号：US06291891B1

公开(公告)日：2001-09-18

申请号：US09228642

申请日：1999-01-12

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC分类号： H01L2348

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

公开(公告)号：US08828886B2

公开(公告)日：2014-09-09

申请号：US13440480

申请日：2012-04-05

申请人： Seiji Samukawa ,  Shigeo Yasuhara ,  Shingo Kadomura ,  Tsutomu Shimayama ,  Hisashi Yano ,  Kunitoshi Tajima ,  Noriaki Matsunaga ,  Masaki Yoshimaru

发明人： Seiji Samukawa ,  Shigeo Yasuhara ,  Shingo Kadomura ,  Tsutomu Shimayama ,  Hisashi Yano ,  Kunitoshi Tajima ,  Noriaki Matsunaga ,  Masaki Yoshimaru

IPC分类号： H01L21/312 ,  C09D183/04 ,  H01L21/02 ,  C23C16/48 ,  C23C16/40

CPC分类号： H01L21/02126 ,  C23C16/401 ,  C23C16/486 ,  H01L21/02216 ,  H01L21/02277

摘要： Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.

摘要翻译： 公开了由包含Si原子，O原子，C原子和H原子的聚合物形成的低介电常数绝缘膜，其包括其中多个具有SiO结构的碱性分子在直链中键合的直链分子，粘合剂 具有连接多个直链分子的SiO结构的分子。 指示线性型SiO结构的信号的面积比为49％以上，表示Si（CH3）的信号的信号量为66％以上。

公开(公告)号：US08536706B2

公开(公告)日：2013-09-17

申请号：US13707359

申请日：2012-12-06

申请人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

公开(公告)号：US08344509B2

公开(公告)日：2013-01-01

申请号：US12652204

申请日：2010-01-05

申请人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US20110108987A1

公开(公告)日：2011-05-12

申请号：US12897941

申请日：2010-10-05

申请人： Hideyuki Tomizawa ,  Tadayoshi Watanabe ,  Noriaki Matsunaga

发明人： Hideyuki Tomizawa ,  Tadayoshi Watanabe ,  Noriaki Matsunaga

IPC分类号： H01L23/532

CPC分类号： H01L23/485 ,  H01L21/76807 ,  H01L21/76846 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, may include a first insulating layer formed on a semiconductor substrate, a contact provided in the first insulating layer, a second dielectric layer formed on the first insulating layer, the second insulating layer having lower dielectric constant than the first dielectric layer, a wiring formed in the second insulating layer and being electrically connected to the contact, a first barrier metal formed on a bottom of the contact and on a side surface of the wiring, and a second barrier metal formed on a side surface of the bottom and on the first barrier metal.

摘要翻译： 半导体器件可以包括形成在半导体衬底上的第一绝缘层，设置在第一绝缘层中的触点，形成在第一绝缘层上的第二绝缘层，第二绝缘层的介电常数比第一绝缘层低， 形成在第二绝缘层中并且与触点电连接的布线，形成在触点的底部上和布线的侧表面上的第一阻挡金属和形成在底部的侧表面上的第二阻挡金属， 在第一个屏障金属上。

公开(公告)号：US20100115479A1

公开(公告)日：2010-05-06

申请号：US12654865

申请日：2010-01-07

申请人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kanji Yoshida ,  Noriaki Matsunaga

发明人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kanji Yoshida ,  Noriaki Matsunaga

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

摘要翻译： 一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

公开(公告)号：US07652351B2

公开(公告)日：2010-01-26

申请号：US11117726

申请日：2005-04-29

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga

IPC分类号： H01L23/58

CPC分类号： H01L21/76877 ,  H01L21/2885 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to an embodiment of the present invention includes a plurality of chip regions and a plurality of chip rings. The plurality of chip regions include semiconductor integrated circuits each having a multilayered wiring structure using a metal wiring, and are formed into independent chips. The plurality of chip rings has the multilayered wiring structure using the metal wiring, and surround the respective chip regions. The plurality of chip rings are electrically connected to one another.

摘要翻译： 根据本发明实施例的半导体器件包括多个芯片区域和多个芯片环。 多个芯片区域包括各自具有使用金属布线的多层布线结构的半导体集成电路，并且形成为独立的芯片。 多个芯片环具有使用金属布线的多层布线结构，并且包围各个芯片区域。 多个芯片环彼此电连接。

公开(公告)号：US07250681B2

公开(公告)日：2007-07-31

申请号：US10939414

申请日：2004-09-14

申请人： Noriaki Matsunaga

发明人： Noriaki Matsunaga

IPC分类号： H01L23/48

CPC分类号： H01L21/76811 ,  H01L21/76801 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05009 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device includes first level wires; a low-dielectric constant film on the first level wires; first flat vias embedded in the low-dielectric constant film connected to the first level wires, each via having a first length in a longitudinal direction of the first level wires and a second length in a orthogonal direction to the first direction on a plane where the first level wires are disposed, aspect ratio of at least one of the first and second lengths to a height perpendicular to the plane is over 1; and second level wires disposed on the low-dielectric constant film connected to the first vias.

摘要翻译： 半导体器件包括一级电线; 第一级导线上的低介电常数膜; 第一平面通孔嵌入到连接到第一电平布线的低介电常数膜中，每个通孔在第一电平布线的纵向上具有第一长度，在平面上在与第一方向正交的方向上具有第二长度， 第一级布线，第一和第二长度至垂直于该平面的高度中的至少一个的纵横比大于1; 以及设置在与第一通孔相连的低介电常数膜上的第二级布线。

公开(公告)号：US20060006547A1

公开(公告)日：2006-01-12

申请号：US10939414

申请日：2004-09-14

申请人： Noriaki Matsunaga

发明人： Noriaki Matsunaga

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76801 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05009 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device includes first level wires; a low-dielectric constant film on the first level wires; first flat vias embedded in the low-dielectric constant film connected to the first level wires, each via having a first length in a longitudinal direction of the first level wires and a second length in a orthogonal direction to the first direction on a plane where the first level wires are disposed, aspect ratio of at least one of the first and second lengths to a height perpendicular to the plane is over 1; and second level wires disposed on the low-dielectric constant film connected to the first vias.

摘要翻译： 半导体器件包括一级电线; 第一级导线上的低介电常数膜; 第一平面通孔嵌入到连接到第一电平布线的低介电常数膜中，每个通孔在第一电平布线的纵向上具有第一长度，在平面上在与第一方向正交的方向上具有第二长度， 第一级布线，第一和第二长度至垂直于该平面的高度中的至少一个的纵横比大于1; 以及设置在与第一通孔相连的低介电常数膜上的第二级布线。