公开(公告)号：US07545037B2

公开(公告)日：2009-06-09

申请号：US11378899

申请日：2006-03-17

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

摘要翻译： 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

公开(公告)号：US20070278657A1

公开(公告)日：2007-12-06

申请号：US11710490

申请日：2007-02-26

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/485 ,  H01L21/50 ,  H01L23/52

CPC分类号： H01L21/76898 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/81136 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack may include a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. Each semiconductor chip may have an active surface, a back surface opposite to the active surface, and a plurality of connection pads arranged in the center of the active surface. At least one through electrode may be formed in the first semiconductor chip and may be connected to at least one of the plurality of connection pads, and a portion of the at least one through electrode may be exposed by the back surface of the first semiconductor chip. The active surface of the first semiconductor chip may be arranged to face the active surface of the second semiconductor chip. The plurality of connection pads of the first semiconductor chip may be electrically connected to the plurality of connection pads of the second semiconductor chip.

摘要翻译： 芯片堆叠可以包括堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片。 每个半导体芯片可以具有有源表面，与有源表面相对的后表面，以及布置在有源表面的中心的多个连接焊盘。 至少一个贯通电极可以形成在第一半导体芯片中并且可以连接到多个连接焊盘中的至少一个，并且至少一个贯通电极的一部分可以被第一半导体芯片的背面曝光 。 第一半导体芯片的有源表面可以布置成面对第二半导体芯片的有源表面。 第一半导体芯片的多个连接焊盘可以电连接到第二半导体芯片的多个连接焊盘。

公开(公告)号：US20070040247A1

公开(公告)日：2007-02-22

申请号：US11503269

申请日：2006-08-14

申请人： Jong-Joo Lee ,  Mee-Hyun Ahn

发明人： Jong-Joo Lee ,  Mee-Hyun Ahn

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49513 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads.

摘要翻译： 本发明提供了各种引线框封装，其中信号连接和固定电压连接被配置为不同以改善连接相对于其分配的功能的相对性能。 信号连接包括一个或多个信号引线和对应的信号接合线的配置，其倾向于减小信号连接器的相对电容，从而提高高速性能。 固定电压连接包括固定电压引线和固定电压接合线的配置，这将降低固定电压连接器的电感，并降低固定电压连接上的噪声，并提高功率输送特性。 相关联的信号和固定电压连接的配置将趋于导致信号连接，其包括与相应的固定电压引线相比更短，更窄和/或更广泛地与半导体芯片的有源表面分离的信号引线。

公开(公告)号：US20070029662A1

公开(公告)日：2007-02-08

申请号：US11335523

申请日：2006-01-20

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/5228 ,  H01L23/5225 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device may have a plurality of dielectric layers and at least one termination circuit line between the dielectric layers. The termination circuit lines may be formed over the active surface of a semiconductor substrate.

摘要翻译： 半导体器件可以具有多个电介质层和介电层之间的至少一个终端电路线。 终端电路线可以形成在半导体衬底的有源表面上。

公开(公告)号：US20060134833A1

公开(公告)日：2006-06-22

申请号：US11289665

申请日：2005-11-28

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC分类号： H01L21/48

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

公开(公告)号：USRE46666E1

公开(公告)日：2018-01-09

申请号：US14215033

申请日：2014-03-16

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/52 ,  H01L23/043 ,  H01L23/31

CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of the board body, and a second power pad, a second ground pad and a second signal pad are disposed on the back surface of the board body. The second power pad, the second ground pad and the second signal pad are electrically connected to the first power pad, the first ground pad and the first signal pad, respectively. An internal terminal interconnection is provided in a bulk region of the board body or on a surface of the board body. The internal terminal interconnection electrically connects the first internal terminal pad to the second internal terminal pad. A semiconductor package employing the package board is also provided.

公开(公告)号：US08643178B2

公开(公告)日：2014-02-04

申请号：US13775580

申请日：2013-02-25

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

摘要翻译： 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

公开(公告)号：US08410611B2

公开(公告)日：2013-04-02

申请号：US13344634

申请日：2012-01-06

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

公开(公告)号：US08319324B2

公开(公告)日：2012-11-27

申请号：US11950990

申请日：2007-12-05

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/36

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L25/18 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311

摘要： Provided are a high I/O semiconductor chip package in which a processor and a memory device are connected to each other via through electrodes and a method of manufacturing the high I/O semiconductor chip package. The high I/O semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, each memory device being arranged in a matrix in chip regions partitioned by a scribe region; a second semiconductor chip stacked on the first semiconductor chip; and a plurality of through electrodes arranged along peripheral portions of the memory devices and connecting the first and second semiconductor chips to the second circuit patterns of the substrate.

摘要翻译： 提供了一种高I / O半导体芯片封装，其中处理器和存储器件通过电极彼此连接，以及制造高I / O半导体芯片封装的方法。 高I ​​/ O半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 第一半导体芯片，包括布置在所述基板上的多个存储器件，每个存储器件以矩阵布置在由划线区域划分的芯片区域中; 堆叠在第一半导体芯片上的第二半导体芯片; 以及沿着存储装置的周边部分布置的多个通孔，并将第一和第二半导体芯片连接到基板的第二电路图案。

公开(公告)号：US20120049352A1

公开(公告)日：2012-03-01

申请号：US13208455

申请日：2011-08-12

申请人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

发明人： Un-Byoung KANG ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

摘要： A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

摘要翻译： 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。