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48 条记录 (耗时 0.029 秒)

    Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
    32.
    发明授权
    Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials 有权
    混合低k互连结构由2个旋涂电介质材料组成

    公开(公告)号：US06677680B2

    公开(公告)日：2004-01-13

    申请号：US09795429

    申请日：2001-02-28

    申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

    IPC分类号： H01L2348

    CPC分类号： H01L21/76835 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76811

    摘要： A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).

    摘要翻译： 提供了一种双镶嵌型金属布线加上低k电介质互连结构，其中导电金属线和通孔内置于混合低k电介质中，该电介质包括两个具有不同原子组成的旋转电介质和至少一个 的两个旋转电介质是多孔的。 用于形成本发明的混合低k电介质的两个旋转电介质各自具有约2.6或更小的介电常数，优选混合结构的每个电介质具有约1.2至约2.2的k。 通过利用本发明的混合低k电介质，获得对金属线电阻（沟槽深度）的优异控制，而不增加成本。 这是在没有使用掩埋蚀刻停止层的情况下实现的，如果存在的话，它将在两个旋转电介质之间形成。 此外，混合低k电介质的旋转电介质具有明显不同的原子组成，使得能够使用底部纺丝电介质（即，通过电介质）控制导体电阻，作为用于上纺丝的固有蚀刻停止层 电介质（即线电介质）。

    Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same
    35.
    发明授权
    Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same 失效
    具有超锐P-N结的半导体装置及其制造方法

    公开(公告)号：US06180444B2

    公开(公告)日：2001-01-30

    申请号：US09025710

    申请日：1998-02-18

    申请人： Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    发明人： Stephen McConnell Gates ,  Roy Edwin Scheuerlein

    IPC分类号： H01L218234

    CPC分类号： H01L29/66136 ,  H01L27/0814 ,  H01L29/861 ,  H01L29/868

    摘要： A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.

    摘要翻译： 诸如PN或PIN结二极管的半导体器件包括具有第一导电类型并且安装在金属地址线上的第一半导体层，以及具有第二导电类型并安装在第一半导体上的第二半导体层 材料。 二极管优选具有基本上不超过约1微米的厚度，并且二极管包括限定在小于约0.1微米厚度的P-N结。 在优选实施例中，该方法包括沉积具有第一导电类型的第一半导体层，沉积第二本征层，退火以将两层转换成多晶层，将第二导电类型的离子注入到第二层中，以及退火以转换 第二层为多晶。 结果是具有超锋利p-n结的二极管。

    Thin film transistors fabricated on plastic substrates
    36.
    发明授权
    Thin film transistors fabricated on plastic substrates 失效
    在塑料基板上制造的薄膜晶体管

    公开(公告)号：US5796121A

    公开(公告)日：1998-08-18

    申请号：US823844

    申请日：1997-03-25

    申请人： Stephen McConnell Gates

    发明人： Stephen McConnell Gates

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/12

    CPC分类号： H01L29/66765 ,  H01L29/78603

    摘要： A thin film transistor is described incorporating a gate electrode, a gate insulating layer, a semiconducting channel layer deposited on top of the gate insulating layer, an insulating encapsulation layer positioned on the channel layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer, all of which are situated on a plastic substrate. By enabling the use of plastics having low glass transition temperatures as substrates, the thin film transistors may be used in large area electronics such as information displays and light sensitive arrays for imaging which are flexible, lighter in weight and more impact resistant than displays fabricated on traditional glass substrates. The thin film transistors are useful in active matrix liquid crystal displays where the plastic substrates are transparent in the visible spectrum. Enablement of the use of such plastics is by way of the use of polymeric encapsulation films to coat the surfaces of the plastic substrates prior to subsequent processing and the use of novel low temperature processes for the deposition of thin film transistor structures.

    摘要翻译： 描述了一种薄膜晶体管，其结合了栅极电极，栅极绝缘层，沉积在栅极绝缘层顶部的半导体沟道层，位于沟道层上的绝缘封装层，源极，漏极和接触层 在每个源极和漏极电极下方并且与至少沟道层接触，所有这些都位于塑料衬底上。 通过使用具有低玻璃化转变温度的塑料作为基板，薄膜晶体管可以用于大面积电子设备中，例如用于成像的信息显示器和光敏阵列，其具有柔性，重量更轻，并且抗冲击性比制造在 传统玻璃基板。 薄膜晶体管可用于有源矩阵液晶显示器，其中塑料基板在可见光谱中是透明的。 使用这种塑料是通过使用聚合物封装膜在随后的处理之前涂覆塑料基板的表面，以及使用用于沉积薄膜晶体管结构的新颖的低温工艺。