公开(公告)号：US4888685A

公开(公告)日：1989-12-19

申请号：US850103

申请日：1986-04-10

申请人： Shigeki Morinaga ,  Mitsuru Watabe

发明人： Shigeki Morinaga ,  Mitsuru Watabe

IPC分类号： G06F13/42 ,  G06F13/12 ,  G06F13/40 ,  G06F15/16 ,  G06F15/177 ,  G06F15/78

CPC分类号： G06F13/4077

摘要： A computer and an input/output device are connected via an interface bus. The input/output device has registers. The computer and the input/output device operate upon the basis of a pair of clock signals. When the input/output device accesses the registers via read and write buses, the buses are precharged during a first period of first clock signal of the pair and controlled by data during a first period of second clock signal of the pair. When the computer accesses the registers via the interface bus, the bus is precharged during the first period of the second clock signal of the pair and controlled by data during the first period of the first clock signal of the pair.

摘要翻译： 计算机和输入/输出设备通过接口总线连接。 输入/输出设备有寄存器。 计算机和输入/输出设备基于一对时钟信号进行操作。 当输入/输出设备通过读和写总线访问寄存器时，总线在该对的第一时钟信号的第一周期期间被预充电，并且在该对的第二时钟信号的第一周期期间被数据控制。 当计算机经由接口总线访问寄存器时，总线在该对的第二时钟信号的第一周期期间被预充电，并且在该对的第一时钟信号的第一周期期间由数据控制。

公开(公告)号：US08332683B2

公开(公告)日：2012-12-11

申请号：US12731442

申请日：2010-03-25

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1/04

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US07711976B2

公开(公告)日：2010-05-04

申请号：US11826136

申请日：2007-07-13

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1/04

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US06390064B2

公开(公告)日：2002-05-21

申请号：US09840065

申请日：2001-04-24

申请人： Katsuji Marumoto ,  Masatoshi Hoshino ,  Ryozo Masaki ,  Minoru Ohsuga ,  Mitsuru Watabe

发明人： Katsuji Marumoto ,  Masatoshi Hoshino ,  Ryozo Masaki ,  Minoru Ohsuga ,  Mitsuru Watabe

IPC分类号： F02D910

CPC分类号： F02D11/105 ,  F02D2041/1419

摘要： An apparatus of controlling an electronically controllable throttle valve for car has a sensor for detecting the opening of the throttle valve and a microcomputer. A throttle valve opening command value is delivered in the form of a digital signal under the control of the microcomputer. The digital command value signal is converted into an analog signal and on the basis of the analog signal and a detected throttle opening, a motor connected to the throttle valve is driven to control the opening thereof.

摘要翻译： 控制电子可控制的汽车节气门的装置具有用于检测节气门和微型计算机的开度的传感器。 在微型计算机的控制下，以数字信号的形式传送节气门开启指令值。 数字指令值信号被转换为模拟信号，并且基于模拟信号和检测到的节气门开度，驱动连接到节流阀的马达来控制其开启。

公开(公告)号：US06343357B1

公开(公告)日：2002-01-29

申请号：US09632332

申请日：2000-08-03

申请人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

发明人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC分类号： G06F1500

CPC分类号： G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

摘要翻译： 采用通用寄存器方法的微型计算机MCU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点 通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。 并且，通过注意代码位来执行编码除法的控制。

公开(公告)号：US06253733B1

公开(公告)日：2001-07-03

申请号：US09531763

申请日：2000-03-20

申请人： Katsuji Marumoto ,  Masatoshi Hoshino ,  Ryozo Masaki ,  Minoru Ohsuga ,  Mitsuru Watabe

发明人： Katsuji Marumoto ,  Masatoshi Hoshino ,  Ryozo Masaki ,  Minoru Ohsuga ,  Mitsuru Watabe

IPC分类号： F02D4120

CPC分类号： F02D11/105 ,  F02D2041/1419

摘要： An apparatus of controlling an electronically controllable throttle valve for car has a sensor for detecting the opening of the throttle valve and a microcomputer. A throttle valve opening command value is delivered in the form of a digital signal under the control of the microcomputer. The digital command value signal is converted into an analog signal and on the basis of the analog signal and a detected throttle opening, a motor connected to the throttle valve is driven to control the opening thereof.

公开(公告)号：US6055960A

公开(公告)日：2000-05-02

申请号：US346578

申请日：1999-07-02

申请人： Katsuji Marumoto ,  Masatoshi Hoshino ,  Ryozo Masaki ,  Minoru Ohsuga ,  Mitsuru Watabe

发明人： Katsuji Marumoto ,  Masatoshi Hoshino ,  Ryozo Masaki ,  Minoru Ohsuga ,  Mitsuru Watabe

IPC分类号： F02D11/10 ,  F02D41/20 ,  F02D45/00 ,  H02P7/29 ,  F02D9/02

CPC分类号： F02D11/105 ,  F02D2041/1419

摘要： An apparatus of controlling an electronically controllable throttle valve for car has a sensor for detecting the opening of the throttle valve and a microcomputer. A throttle valve opening command value is delivered in the form of a digital signal under the control of the microcomputer. The digital command value signal is converted into an analog signal and on the basis of the analog signal and a detected throttle opening, a motor connected to the throttle valve is driven to control the opening thereof.

公开(公告)号：US5991545A

公开(公告)日：1999-11-23

申请号：US478730

申请日：1995-06-07

申请人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

发明人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC分类号： G06F9/28 ,  G06F7/483 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535 ,  G06F7/537 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

摘要翻译： 这里公开了采用通用寄存器方法的微计算机MCU。 微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过 采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US5642499A

公开(公告)日：1997-06-24

申请号：US223834

申请日：1994-04-06

申请人： Mamoru Ohba ,  Shigeki Morinaga ,  Mitsuru Watabe ,  Hiroyuki Kida

发明人： Mamoru Ohba ,  Shigeki Morinaga ,  Mitsuru Watabe ,  Hiroyuki Kida

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F11/28 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F9/461 ,  G06F9/30025 ,  G06F9/3861 ,  G06F9/3885

摘要： In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.

摘要翻译： 在具有中央处理单元（CPU）的协处理器系统中，当CPU向FPU发出保存命令时，通过总线彼此耦合的浮点处理单元（FPU）和存储器（RAM），FPU鉴别 FPU在接收到保存命令及其内部状态时执行的当前命令的属性，即长命令或短命令。 响应于鉴别结果，FPU一旦中断当前命令的执行，开始执行接收到的保存命令，当前命令为长命令，并且FPU在执行完成后执行接收到的保存命令 的当前命令，如果当前命令是一个短命令。 基于执行命令所需的时间和为此提供的预定标准，预先确定命令的属性。

公开(公告)号：US5530965A

公开(公告)日：1996-06-25

申请号：US517151

申请日：1995-08-21

申请人： Shumpei Kawasaki ,  Kaoru Fukada ,  Mitsuru Watabe ,  Kouki Noguchi ,  Kiyoshi Matsubara ,  Isamu Mochizuki ,  Kazufumi Suzukawa ,  Shigeki Masumura ,  Yasushi Akao ,  Eiji Sakakibara

发明人： Shumpei Kawasaki ,  Kaoru Fukada ,  Mitsuru Watabe ,  Kouki Noguchi ,  Kiyoshi Matsubara ,  Isamu Mochizuki ,  Kazufumi Suzukawa ,  Shigeki Masumura ,  Yasushi Akao ,  Eiji Sakakibara

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F13/42 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F15/7832 ,  G06F13/4239 ,  G06F15/786

摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

摘要翻译： 一种易于使用和直接连接到动态和静态RAM以及其他外围电路等存储器的微型计算机。 微型计算机具有选通信号输出端子CASH *，CASL *和RAS *，用于直接连接到动态RAM，以及芯片选择信号输出端子CS0 *至CS6 *，用于与选通信号输出的输出并行输出芯片选择信号 终端。 微型计算机还包括用于根据需要输出未复用或多路复用的地址信号的地址输出端子和用于选择性地输出地址信号以符合多总线接口方案的数据I / O端子。