公开(公告)号：US20090116309A1

公开(公告)日：2009-05-07

申请号：US12348306

申请日：2009-01-04

申请人： SATORU HANZAWA ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

发明人： SATORU HANZAWA ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C7/1027 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/028 ,  G11C2207/002

摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中提供可以根据读使能信号RD1，RD2设置两种电流之一的电流控制电路IC。 在定时控制器的控制下，在脉冲串读取操作中的周期数对应的定时产生读使能信号RD1，RD2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD1被设置为较大，而当前控制电路IC中的电流在下一个和随后的脉冲串中被RD2设置得较小 读周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

公开(公告)号：US20090102524A1

公开(公告)日：2009-04-23

申请号：US12208978

申请日：2008-09-11

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C19/00

摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.

摘要翻译： 公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从 第一时钟信号的上升沿大约为td = m.T1 + n。（T2 / L）的延迟td。 定时控制电路包括粗延迟电路和精细延迟电路。 粗延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量近似为m.T1的粗定时信号。 精细延迟电路包括并联设置的L个多相时钟控制延迟电路，延迟n.T2 / L，通过L相第二时钟组的相应时钟对粗略定时信号进行采样的定时， 或者产生延迟脉冲，从而产生精细定时信号。

公开(公告)号：US07495943B2

公开(公告)日：2009-02-24

申请号：US11655945

申请日：2007-01-22

申请人： Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C5/02

CPC分类号： G11C8/12 ,  G11C5/025 ,  G11C5/04 ,  G11C7/18 ,  G11C11/4097 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/10814 ,  H01L2224/4826 ,  H01L2924/13091 ,  H01L2924/00

摘要： If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of a 1:2 shape. In addition, such conventional layout of memory cell blocks to form the 1:2 shape causes the area of a peripheral circuit region to be limited by the memory blocks, pads to be arranged collectively in the central section of the chip, and wiring to become dense during the enclosure of the chip in the package.In this invention, therefore, four memory blocks, BANK0, BANK1, BANK2, BANK3, BANK3, are constructed into an L shape and then these memory blocks are properly combined and arranged to construct a chip of nearly a 1:2 shape in terms of aspect ratio.

摘要翻译： 如果通过使用纵横比为1:2的存储单元，以常规方式布置存储单元块以创建具有2的奇数功率的容量的存储芯片，则芯片将采取1：1的形状并变得难以 以1：2的形状包装。 此外，存储单元块的这种传统布局形成1：2形状会导致外围电路区域的区域受到存储块的限制，焊盘将被集中布置在芯片的中心部分中，并且布线成为 密封在芯片封装中的封装。 因此，在本发明中，将四个存储器块BANK0，BANK1，BANK2，BANK3，BANK3构造成L形，然后这些存储块被适当地组合并布置成构成近似1：2形状的芯片 长宽比。

公开(公告)号：US07489588B2

公开(公告)日：2009-02-10

申请号：US11924353

申请日：2007-10-25

申请人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

IPC分类号： G11C7/08

CPC分类号： G11C7/1027 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/028 ,  G11C2207/002

摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中提供可以根据读使能信号RD1，RD2设置两种电流之一的电流控制电路IC。 在定时控制器的控制下，在脉冲串读取操作中的周期数对应的定时产生读使能信号RD1，RD2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD1被设置为较大，而当前控制电路IC中的电流在下一个和随后的脉冲串中被RD2设置得较小 读周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

公开(公告)号：US07345938B2

公开(公告)日：2008-03-18

申请号：US11797984

申请日：2007-05-09

申请人： Riichiro Takemura ,  Kiyoo Itoh ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Katsutaka Kimura

发明人： Riichiro Takemura ,  Kiyoo Itoh ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Katsutaka Kimura

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C5/025 ,  G11C5/14 ,  G11C7/06 ,  G11C7/08 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065 ,  H01L27/0207 ,  H01L27/10894

摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

摘要翻译： 一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。 用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。 使用网状电力线电路提供过驱动的可能性。 通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。 驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。

公开(公告)号：US20080002448A1

公开(公告)日：2008-01-03

申请号：US11896802

申请日：2007-09-06

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882

摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

摘要翻译： 在追求微型制造的大规模集成DRAM中，数据线字线耦合电容在配对数据线之间不平衡。 数据线字线的不平衡意味着当数据线经受放大时产生大的噪声，这极有可能引起数据线上非常小的信号的恶化和数据的错误放大。 连接到连接到一个数据线的多个存储单元的多个字线中的一个或几个字线交替地连接到布置在存储器阵列的相对侧上的子字驱动器阵列。 当数据线被放大时，正和负字线噪声分量在子字驱动器中彼此抵消，从而可以减小字线噪声。 因此，可以防止由读出放大器读出的信号劣化，从而提高存储器操作的可靠性。

公开(公告)号：US07304910B1

公开(公告)日：2007-12-04

申请号：US11467793

申请日：2006-08-28

申请人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

IPC分类号： G11C8/18 ,  G11C5/14

CPC分类号： G11C7/1027 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/028 ,  G11C2207/002

摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中设置有能够根据读使能信号RD1，RD2设定两种电流之一的电流控制电路IC。 在定时控制器的控制下，在与脉冲串读取操作中的周期数相对应的定时，生成读使能信号RD 1，RD 2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD 1被设置为较大，而当前控制电路IC中的电流被下一个的RD 2设置得较小时， 随后的突发读取周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

公开(公告)号：US07262983B2

公开(公告)日：2007-08-28

申请号：US11652012

申请日：2007-01-11

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C5/02 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US20070147152A1

公开(公告)日：2007-06-28

申请号：US11706409

申请日：2007-02-15

申请人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Shinichi Miyatake ,  Takeshi Sakata ,  Riichiro Takemura ,  Hiromasa Noda ,  Kazuhiko Kajigaya

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C5/063 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C29/1201 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10897

摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

摘要翻译： 本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。 由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。 此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。 此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

公开(公告)号：US07193884B2

公开(公告)日：2007-03-20

申请号：US11280170

申请日：2005-11-17

申请人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

IPC分类号： G11C11/24

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882

摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.

摘要翻译： 从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压 晶体管经由存储单元晶体管写入电容器的存储节点。 此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且 根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。