公开(公告)号：US09704853B2

公开(公告)日：2017-07-11

申请号：US13671506

申请日：2012-11-07

申请人： Hubert M. Bode ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Hubert M. Bode ,  Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L21/761 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/092

CPC分类号： H01L27/04 ,  H01L21/02381 ,  H01L21/761 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7817 ,  H01L29/7835

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

公开(公告)号：US09620496B2

公开(公告)日：2017-04-11

申请号：US14644041

申请日：2015-03-10

申请人： Weize Chen ,  Hubert M. Bode ,  Andreas Laudenbach ,  Kurt U. Neugebauer ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Andreas Laudenbach ,  Kurt U. Neugebauer ,  Patrice M. Parris

IPC分类号： H02H3/00 ,  H02H3/02 ,  H02H9/04 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8222

CPC分类号： H01L27/0248 ,  H01L21/8222 ,  H01L27/0259 ,  H01L27/067

摘要： Protection circuits, device structures and related fabrication methods are provided. An exemplary protection circuit includes a first protection arrangement and a second protection arrangement. The first protection arrangement includes a first transistor having a first collector, a first emitter, and a first base coupled to the first emitter at a first node, and a second transistor having a second collector, a second emitter, and a second base coupled to the second emitter at a second node, the second collector being coupled to the first collector at a third node. The second protection arrangement is coupled electrically in series between the second node and a fourth node. The protection circuit further includes a first diode coupled between the third node and the fourth node.

公开(公告)号：US09599587B2

公开(公告)日：2017-03-21

申请号：US14478149

申请日：2014-09-05

申请人： Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza ,  Md M. Hoque ,  John M. McKenna

发明人： Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza ,  Md M. Hoque ,  John M. McKenna

IPC分类号： G11C16/04 ,  G01N27/414 ,  H01L27/115 ,  H01L49/02 ,  H01L29/66 ,  H01L29/788 ,  H01L29/94 ,  G05F1/575 ,  H01L21/28 ,  H01L23/522

CPC分类号： G01N27/4148 ,  G05F1/575 ,  G11C16/0416 ,  H01L21/28035 ,  H01L23/5223 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40 ,  H01L28/60 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

公开(公告)号：US09559097B2

公开(公告)日：2017-01-31

申请号：US14507063

申请日：2014-10-06

申请人： Patrice M. Parris ,  Hubert M. Bode ,  Weize Chen ,  Richard J DeSouza ,  Andreas Laudenbach ,  Kurt U. Neugebauer

发明人： Patrice M. Parris ,  Hubert M. Bode ,  Weize Chen ,  Richard J DeSouza ,  Andreas Laudenbach ,  Kurt U. Neugebauer

IPC分类号： H01L27/07 ,  H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7823 ,  H01L21/761 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

摘要翻译： 在非隔离功率晶体管器件和电子设备中配置有一个或多个集成击穿保护二极管的半导体器件，以及用于制造器件的方法。

公开(公告)号：US20160370314A1

公开(公告)日：2016-12-22

申请号：US15251141

申请日：2016-08-30

申请人： Patrice M. Parris ,  Weize Chen ,  Richard J. de Souza ,  Jose Fernandez Villasenor ,  Md M. Hoque ,  David E. Niewolny ,  Raymond M. Roop

发明人： Patrice M. Parris ,  Weize Chen ,  Richard J. de Souza ,  Jose Fernandez Villasenor ,  Md M. Hoque ,  David E. Niewolny ,  Raymond M. Roop

IPC分类号： G01N27/414 ,  G01N27/28 ,  B01L3/00

CPC分类号： G01N27/4148 ,  B01L3/5027 ,  B01L3/502715 ,  B01L3/50273 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/04 ,  B01L2300/041 ,  B01L2300/0645 ,  B01L2300/0887 ,  B01L2400/0415 ,  B01L2400/0418 ,  G01N27/28 ,  G01N27/414 ,  H01L21/67259 ,  H01L29/4933 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7833 ,  H01L31/119

摘要： Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

摘要翻译： 保护传感器场效应晶体管（SFET）。 SFET包括半导体衬底，场效应晶体管和感测电极。 SFET还包括由半导体衬底支撑的分析物接收区域，与感测电极接触，并被配置为接收分析物流体。 分析物接收区域至少部分封闭。 在一些实施方案中，分析物接收区域可以是在分析物入口和分析物出口之间延伸的封闭分析物通道。 在这些实施例中，封闭的分析物通道延伸使得分析物入口和分析物出口与感测电极间隔开。 在一些实施例中，SFET包括至少部分地包围分析物接收区并由可溶于分析物流体内的覆盖材料形成的覆盖结构。 这些方法包括制造SFET的方法。

公开(公告)号：US09478467B2

公开(公告)日：2016-10-25

申请号：US14543668

申请日：2014-11-17

申请人： Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L21/82 ,  H01L21/8236 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/8236 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/0883

摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material. Prior to removing the patterned layer of masking material, the fabrication process etches the layer of gate electrode material to form a gate structure overlying the channel region using the patterned layer of masking material as an etch mask and forms extension regions in the well region using the patterned layer of masking material as an implant mask. Thereafter, the patterned layer of masking material is removed after forming the gate structure and the extension regions.

摘要翻译： 提供半导体器件结构和相关的制造方法。 示例性的制造方法包括形成覆盖半导体衬底的栅电极材料层，形成覆盖栅极电极材料的掩模材料层，以及图案化掩模材料层，以限定半导体衬底的阱区域内的沟道区域， 构成栅电极材料。 在去除掩模材料的图案化层之前，制造工艺蚀刻栅极电极材料层，以形成覆盖沟道区域的栅极结构，使用图案化的掩模材料层作为蚀刻掩模，并使用 掩模材料的图案化层作为植入物掩模。 此后，在形成栅极结构和延伸区域之后去除掩模材料的图案化层。

公开(公告)号：US09437701B2

公开(公告)日：2016-09-06

申请号：US14524172

申请日：2014-10-27

申请人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/823443 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

摘要翻译： 具有反掺杂导电栅极的集成电路器件。 这些器件具有具有衬底表面的半导体衬底。 器件还具有第一导电类型的第一阱，第二导电类型的源极和第二导电类型的漏极。 通道在源极和漏极之间延伸。 导电栅极延伸穿过通道。 导电栅极包括第一导电类型的第一栅极区域和第二栅极区域以及第一导电类型的第三栅极区域。 第三栅极区域在第一和第二栅极区域之间延伸。 器件还包括在导电栅极和衬底之间延伸并且还包括与第一，第二和第三栅极区域电连通的硅化物区域的栅极电介质。 这些方法包括制造器件的方法。

公开(公告)号：US09423376B2

公开(公告)日：2016-08-23

申请号：US14265622

申请日：2014-04-30

申请人： Md M. Hoque ,  Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza

发明人： Md M. Hoque ,  Patrice M. Parris ,  Weize Chen ,  Richard J. De Souza

IPC分类号： G01N27/414 ,  H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28 ,  H01L27/115

CPC分类号： G01N27/4148 ,  H01L21/28282 ,  H01L27/11531 ,  H01L29/66 ,  H01L29/66409 ,  H01L29/78 ,  H01L29/788

摘要： A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.

摘要翻译： 差分对检测电路（300）包括用于将参考晶体管（350）和化学敏感晶体管（351）单独编程为期望阈值电压Vt的控制栅极（306,316），以消除晶体管之间的失配，以便 提高感测电路的灵敏度和/或精度，而不增加电路尺寸。

公开(公告)号：US20160118469A1

公开(公告)日：2016-04-28

申请号：US14524172

申请日：2014-10-27

申请人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. de Souza ,  Md M. Hoque ,  Patrice M. Parris

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/823443 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

摘要翻译： 具有反掺杂导电栅极的集成电路器件。 这些器件具有具有衬底表面的半导体衬底。 器件还具有第一导电类型的第一阱，第二导电类型的源极和第二导电类型的漏极。 通道在源极和漏极之间延伸。 导电栅极延伸穿过通道。 导电栅极包括第一导电类型的第一栅极区域和第二栅极区域以及第一导电类型的第三栅极区域。 第三栅极区域在第一和第二栅极区域之间延伸。 器件还包括在导电栅极和衬底之间延伸并且还包括与第一，第二和第三栅极区域电连通的硅化物区域的栅极电介质。 这些方法包括制造器件的方法。

公开(公告)号：US09129990B2

公开(公告)日：2015-09-08

申请号：US13538529

申请日：2012-06-29

申请人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

发明人： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC分类号： H01L27/088 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L21/761 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H03K17/687 ,  H03K17/74

CPC分类号： H01L21/823481 ,  H01L21/761 ,  H01L21/823418 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H03K17/6871 ,  H03K17/74 ,  H03K2217/0018 ,  H03K2217/0036

摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

摘要翻译： 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第二导电类型的漏极区域，二极管电路连接在隔离结构和漏极区域之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。