公开(公告)号：US20190305094A1

公开(公告)日：2019-10-03

申请号：US15937068

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01L29/417 ,  H01L29/737 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/285

Abstract: In certain aspects, a heterojunction bipolar transistor (HBT) comprises a collector mesa, a base mesa on the collector mesa, and an emitter mesa on the base mesa. The base mesa has a tapered sidewall tapering from a wide bottom to a narrow top. The HBT further comprises a collector contact on a portion of the collector mesa and extending to a portion of the tapered sidewall of the base mesa.

公开(公告)号：US20190027576A1

公开(公告)日：2019-01-24

申请号：US15710271

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO

IPC: H01L29/66 ,  H01L29/778

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) device may include a substrate. A composite multilayer channel material may be on the substrate. The composite multilayer channel material may include a channel region, a source region, and a drain region. A gate may be on the channel region of the composite multilayer channel material.

公开(公告)号：US20180254194A1

公开(公告)日：2018-09-06

申请号：US15450605

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L21/322 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

公开(公告)号：US20160336324A1

公开(公告)日：2016-11-17

申请号：US14713712

申请日：2015-05-15

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0928 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823814 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66356 ,  H01L29/66977 ,  H01L29/7391

Abstract: A vertically integrated transistor device increases the effective active area of the device to improve the performance characteristics of the device. The transistor device may include a plurality of gate elements, a plurality of source-drain elements extending parallel to the plurality of gate elements and horizontally spaced therefrom; and a plurality of fin elements extending parallel to the plurality of gate elements and vertically spaced therefrom, wherein each of the plurality of fin elements is horizontally spaced a first distance from each of the other ones of the plurality of fin elements.

Abstract translation: 垂直集成的晶体管器件增加了器件的有效有效面积，以提高器件的性能特性。 晶体管器件可以包括多个栅极元件，多个源极 - 漏极元件，其平行于多个栅极元件延伸并与之水平间隔开; 以及与所述多个栅极元件平行延伸并且与其垂直间隔开的多个翅片元件，其中所述多个翅片元件中的每一个与所述多个翅片元件中的每一个中的每一个水平间隔开第一距离。

公开(公告)号：US20160254443A1

公开(公告)日：2016-09-01

申请号：US15149396

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun ZHU ,  Xia LI ,  Seung Hyuk KANG

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/15 ,  G11C11/155 ,  G11C11/161 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An in-process magnetic layer having an in-process area dimension is formed with a chemically damaged region at a periphery. At least a portion of the chemically damaged region is transformed to a chemically modified peripheral portion that is non-ferromagnetic. Optionally, the transforming is by oxidation, nitridation or fluorination, or combinations of the same.

Abstract translation: 具有处理区域尺寸的过程中的磁性层在周边形成化学损伤区域。 化学损伤区域的至少一部分被转化为非铁磁性的化学改性的周边部分。 任选地，转化是通过氧化，氮化或氟化，或其组合。

公开(公告)号：US20160254056A1

公开(公告)日：2016-09-01

申请号：US14633793

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xiao LU ,  Xiaonan CHEN ,  Zhongze WANG

IPC: G11C16/10 ,  G11C17/18 ,  G11C16/04 ,  G11C17/16

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/42348 ,  H01L29/7923

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

Abstract translation: 根据本公开的一些示例的用于一次可编程（OTP）存储器的半导体器件包括栅极，栅极下方的介电区域，介质区域下方的偏移并且偏移到一侧的源极端子，电介质下方的漏极端子 并且偏移到与源极端子相反的一侧，在能够编程半导体器件的电介质区域中的漏极侧电荷阱，以及与漏极侧电荷阱相对的电介质区域中的源极电荷陷阱，并且能够对半导体 设备。

公开(公告)号：US20160005849A1

公开(公告)日：2016-01-07

申请号：US14321539

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Ming CAI

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/201 ,  H01L29/205 ,  H01L21/762 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7789 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/151 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7781 ,  H01L29/7783 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An inner fin of a high bandgap material is on a substrate, having two vertical faces, and is surrounded by a carrier redistribution fin of a low bandgap material. The inner fin and the carrier redistribution fin have two vertical interfaces. The carrier redistribution fin has a thickness and a bandgap relative to the bandgap of the inner fin that establishes, along the two vertical interfaces, an equilibrium of a corresponding two two-dimensional electron gasses.

公开(公告)号：US20250107157A1

公开(公告)日：2025-03-27

申请号：US18475053

申请日：2023-09-26

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Biswa Ranjan PANDA

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An electronic device having one or more Gate-All-Around GAA transistors is disclosed. At least one of the one or more GAA transistors comprises one or more inner gate structures having a work function metal bounded by a gate dielectric; and one or more inner gate spacers associated with the one or more inner gate structures, wherein each of the one or more inner gate structures has a generally concave outer edge that conforms to a generally convex inner edge of an associated inner gate spacer of the one or more inner gate spacers.

公开(公告)号：US20240429141A1

公开(公告)日：2024-12-26

申请号：US18340556

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xuefeng ZHANG ,  Aniket PATIL

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

Abstract: A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.

公开(公告)号：US20240319455A1

公开(公告)日：2024-09-26

申请号：US18607170

申请日：2024-03-15

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Aniket PATIL ,  Dongming HE

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4245 ,  G02B6/4248 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16155 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2924/1427 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.