利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

122 条记录 (耗时 0.034 秒)

    Method for reducing dielectric overetch when making contact to conductive features
    31.
    发明授权
    Method for reducing dielectric overetch when making contact to conductive features 有权
    在与导电特征接触时减小介质过蚀刻的方法

    公开(公告)号：US08497204B2

    公开(公告)日：2013-07-30

    申请号：US13087646

    申请日：2011-04-15

    申请人： Christopher J. Petti

    发明人： Christopher J. Petti

    IPC分类号： H01L21/311

    CPC分类号： H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76829 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种方法，其包括：在第一介电材料上方形成多个导电或半导体特征; 在导电或半导体特征之上沉积第二电介质材料; 蚀刻所述第二电介质材料中的空隙，其中所述蚀刻在所述第一和第二电介质材料之间是选择性的，并且所述蚀刻停止在所述第一电介质材料上; 以及暴露导电或半导体特征的一部分。 提供了许多其他方面。

    Method for forming polycrystalline thin film bipolar transistors
    34.
    发明授权
    Method for forming polycrystalline thin film bipolar transistors 有权
    多晶薄膜双极晶体管的形成方法

    公开(公告)号：US07855119B2

    公开(公告)日：2010-12-21

    申请号：US11763876

    申请日：2007-06-15

    申请人： Christopher J. Petti ,  S. Brad Herner

    发明人： Christopher J. Petti ,  S. Brad Herner

    IPC分类号： H01L21/331 ,  H01L29/70

    CPC分类号： H01L29/66265 ,  G11C17/16 ,  H01L29/7317

    摘要： A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49phase titanium silicide.

    摘要翻译： 描述了一种用于形成半导体器件的方法，该半导体器件包括具有基极区域，发射极区域和集电极区域的双极晶体管，其中，所述基极区域包括通过使硅，锗或硅锗与硅化物，锗化锗接触而形成的多晶半导体材料 或锗化锗。 发射极区域和集电极区域也可以由通过使硅，锗或硅锗与硅化物，锗化锗或锗化锗形成金属接触而形成的多晶半导体材料形成。 多晶半导体材料优选为与C49相钛硅化物接触形成的硅化多晶硅。

    NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL
    35.
    发明申请
    NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL 有权
    包含二极管和电阻切换材料的非易失性存储单元

    公开(公告)号：US20100302836A1

    公开(公告)日：2010-12-02

    申请号：US12855462

    申请日：2010-08-12

    申请人： S. Brad Herner ,  Tanmay Kumar ,  Christopher J. Petti

    发明人： S. Brad Herner ,  Tanmay Kumar ,  Christopher J. Petti

    IPC分类号： G11C11/00 ,  H01L21/16

    CPC分类号： H01L27/249 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

    摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.

    摘要翻译： 在形成于衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NixOy，NbxOy，TixOy，HfxOy，AlxOy，MgxOy，CoxOy，CrxOy ，VxOy，ZnxOy，ZrxOy，BxNy和AlxNy。 在优选实施例中，二极管形成为设置在导体之间的垂直支柱。 可以堆叠多个存储器级别以形成单片三维存储器阵列。 在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。 本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

    METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE
    36.
    发明申请
    METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE 有权
    在平面表面上使用介质蚀刻停止来减少介电覆盖的方法

    公开(公告)号：US20100297834A1

    公开(公告)日：2010-11-25

    申请号：US12849292

    申请日：2010-08-03

    申请人： Samuel V. Dunton ,  Christopher J. Petti ,  Usha Raghuram

    发明人： Samuel V. Dunton ,  Christopher J. Petti ,  Usha Raghuram

    IPC分类号： H01L21/20 ,  H01L21/31

    CPC分类号： H01L27/1021 ,  H01L21/76802 ,  H01L21/76829 ,  Y10S438/90

    摘要： A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

    摘要翻译： 基本平坦的表面共同导电或半导体特征和介电蚀刻停止材料。 不同于介电蚀刻停止材料的第二电介质材料沉积在基本平坦的表面上。 选择性蚀刻蚀刻第二介电材料中的孔或沟槽，使得蚀刻停止在导电或半导体特征和电介质蚀刻停止材料上。 在优选实施例中，通过将导电或半导体特征之间的间隙填充到诸如氧化物的第一电介质，使氧化物凹陷，用第二电介质（例如氮化物）填充，然后平坦化以共存氮化物和导电或 半导体功能。

    Method to form low-defect polycrystalline semiconductor material for use in a transistor
    39.
    发明授权
    Method to form low-defect polycrystalline semiconductor material for use in a transistor 有权
    形成用于晶体管的低缺陷多晶半导体材料的方法

    公开(公告)号：US07790534B2

    公开(公告)日：2010-09-07

    申请号：US11763671

    申请日：2007-06-15

    申请人： S. Brad Herner ,  Christopher J. Petti

    发明人： S. Brad Herner ,  Christopher J. Petti

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L27/24 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/6675 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors.

    摘要翻译： 描述了一种用于形成其多晶半导体材料中具有电流切换区域的薄膜晶体管的方法，其已经与硅化钛，硅化钛 - 锗化锗或锗化锗接触而结晶化。 在最小尺寸上形成特征尺寸不超过0.25微米的硅化钛，硅化钛 - 锗化锗或锗锗。 小特征尺寸倾向于抑制从C49到C54相钛硅化物的相变。 硅化钛的C49相具有与硅非常接近的晶格匹配，因此在形成硅时提供了硅的结晶模板，从而形成大晶粒，低缺陷硅。 在结晶过程中，钛不会通过硅迁移，限制了金属污染的危险。 在优选实施例中，如此形成的晶体管可以是例如场效应晶体管或双极结型晶体管。

    Method for fabricating pitch-doubling pillar structures
    40.
    发明授权
    Method for fabricating pitch-doubling pillar structures 有权
    制造俯仰倍增柱结构的方法

    公开(公告)号：US07759201B2

    公开(公告)日：2010-07-20

    申请号：US12000758

    申请日：2007-12-17

    申请人： Christopher J. Petti ,  Steven J. Radigan

    发明人： Christopher J. Petti ,  Steven J. Radigan

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/102 ,  H01L21/0337

    摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔开的特征，在所述至少两个特征上形成侧壁间隔物，填充第一侧壁 第一特征上的间隔物和具有填充物特征的第二特征上的第二侧壁间隔物，选择性地移除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且蚀刻至少一个装置 层，使用第一特征，填充特征和第二特征作为掩模。