公开(公告)号：US20190116669A1

公开(公告)日：2019-04-18

申请号：US16217753

申请日：2018-12-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yushuang YAO ,  Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Francis J. CARNEY ,  Yusheng LIN

IPC: H05K1/18 ,  H05K1/03 ,  H01L23/48 ,  H05K3/34 ,  H05K1/09 ,  H05K1/02 ,  H05K3/40

Abstract: One illustrative method embodiment includes: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.

公开(公告)号：US20190103338A1

公开(公告)日：2019-04-04

申请号：US16206057

申请日：2018-11-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Soon Wei WANG ,  Hoe Kit Liew How Kat LEY

IPC: H01L23/433 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495

Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

公开(公告)号：US20170170084A1

公开(公告)日：2017-06-15

申请号：US15341367

申请日：2016-11-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yushuang YAO ,  Chee Hiong CHEW ,  Atapol PRAJUCKAMOL

IPC: H01L23/053 ,  H01L23/18 ,  H01L23/498 ,  H01L23/08

Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.

公开(公告)号：US20150364847A1

公开(公告)日：2015-12-17

申请号：US14703002

申请日：2015-05-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yushuang YAO ,  Chee Hiong CHEW ,  Atapol PRAJUCKAMOL

IPC: H01R13/05

CPC classification number: H01R13/05 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01R12/57 ,  H01R12/585 ,  H01R43/02 ,  H01R43/16 ,  H01L2924/00014

Abstract: A pin for a semiconductor package includes an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver. A lower portion of the pin is configured to flex to allow an upper portion of the pin to move towards an upper contact surface of a horizontal base of the pin in response to a pressure applied along a direction collinear with a longest length of the pin towards the upper contact surface of the horizontal base when the pin is inserted into a pin receiver. Some implementations of pins include a vertical stop to stop movement of the pin when a surface of the vertical stop contacts the upper contact surface of the horizontal base. Varying implementations of pins include: two curved legs and one vertical stop; two partially curved legs and no vertical stop, and; a single leg bent into an N-shape.

Abstract translation: 用于半导体封装的引脚包括具有被配置为与引脚接收器机械和电耦合的接触表面的上接触部分。 销的下部被构造为弯曲以允许销的上部部分响应于沿与销的最长长度共线的方向施加的压力而朝销的水平底座的上接触表面移动，朝向 当销插入针式接收器时，水平底座的上接触面。 销的一些实施方案包括垂直停止以在垂直止动件的表面接触水平底座的上接触表面时停止销的运动。 销的不同实现包括：两个弯曲的腿和一个垂直停止; 两个部分弯曲的腿，没有垂直的停止，和; 单腿弯曲成N形。

公开(公告)号：US20250118640A1

公开(公告)日：2025-04-10

申请号：US18987230

申请日：2024-12-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yusheng LIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

Abstract: Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.

公开(公告)号：US20240290758A1

公开(公告)日：2024-08-29

申请号：US18398499

申请日：2023-12-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/071 ,  H01L23/367 ,  H01L24/32 ,  H01L25/50 ,  H01L2224/32245

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

公开(公告)号：US20240290757A1

公开(公告)日：2024-08-29

申请号：US18174837

申请日：2023-02-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yusheng LIN

IPC: H01L25/07 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/071 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/538 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/38 ,  H01L2224/40101 ,  H01L2224/40105 ,  H01L2224/40139 ,  H01L2224/40147 ,  H01L2224/4103 ,  H01L2224/4112 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8493

Abstract: A transistor configured for higher power can be constructed using multiple transistor dies coupled in parallel. This approach of distributing power and heat over multiple transistor dies can allow each transistor die to be made smaller, which can be helpful in improving yield. This is especially true for emerging technologies, such as silicon carbide (SiC). Power modules for power conversion may require a plurality of these multi-die transistors in a package. A package that accommodates the numerous connections required for a multi-die power module is disclosed. The package utilizes a lead frame to provide a three-dimensional sandwich structure in which multiple dies are positioned between two direct bonded copper (DBC) substrates.

公开(公告)号：US20240258181A1

公开(公告)日：2024-08-01

申请号：US18160450

申请日：2023-01-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yushuang YAO ,  Vemmond Jeng Hung NG

IPC: H01L23/13 ,  B32B3/02 ,  B32B9/00 ,  B32B9/04 ,  B32B15/20 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/13 ,  B32B3/02 ,  B32B9/005 ,  B32B9/041 ,  B32B15/20 ,  H01L21/4871 ,  H01L23/3735 ,  B32B2250/03 ,  B32B2250/40 ,  B32B2307/206 ,  B32B2457/00

Abstract: Implementations of a substrate may include an electrically insulative layer having a first largest planar side and a second largest planar side opposing the first largest planar side; a first electrically conductive layer coupled to the first largest planar side and including a first scalloped edge having a first pattern; and a second electrically conductive layer coupled to the second largest planar side and including a second scalloped edge having a second pattern. The first pattern and the second pattern may alternate along at least one edge of the first largest planar side and at least one edge of the second largest planar side, respectively.

公开(公告)号：US20240203846A1

公开(公告)日：2024-06-20

申请号：US18595569

申请日：2024-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/40 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/80 ,  H01L25/0657

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20240038632A1

公开(公告)日：2024-02-01

申请号：US17814949

申请日：2022-07-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yushuang YAO

IPC: H01L23/473 ,  H01L25/07 ,  H01L23/00 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/473 ,  H01L25/072 ,  H01L24/40 ,  H01L23/3735 ,  H01L21/4807 ,  H01L2224/40155 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A method includes disposing at least one power device between a first direct bonded metal (DBM) substrate and a second DMB substrate and thermally coupling a plurality of pipes to a top side of the first DBM substrate opposite a side of the first DBM substrate with the at least one power device. The plurality of pipes is configured to carry cooling fluids in thermal contact with the first DBM substrate.