公开(公告)号：US10002968B2

公开(公告)日：2018-06-19

申请号：US13710929

申请日：2012-12-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/786 ,  H01L27/1225

Abstract: A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common. At least one of semiconductor films used in the first transistor and the second transistor is an oxide semiconductor film. With the use of the oxide semiconductor film as the semiconductor film in the transistor, high field-effect mobility and high-speed operation can be achieved. Since the first transistor and the second transistor are stacked and have the gate electrode in common, the area of a region where the transistors are disposed can be reduced.

公开(公告)号：US09912897B2

公开(公告)日：2018-03-06

申请号：US15149289

申请日：2016-05-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Seiichi Yoneda

IPC: H04N5/378 ,  H04N5/3745 ,  H04N5/374 ,  H04N5/376 ,  H01L29/786 ,  H01L29/24 ,  H01L31/0272 ,  H01L31/032 ,  H01L27/146 ,  H01L27/12

CPC classification number: H04N5/378 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14696 ,  H01L29/24 ,  H01L29/7869 ,  H01L31/0272 ,  H01L31/0322 ,  H02S40/44 ,  H04N5/3742 ,  H04N5/37455 ,  H04N5/37457 ,  H04N5/3765

Abstract: An imaging device in which signals can be read out accurately at high speed is provided. The imaging device includes a plurality of pixels arranged in a matrix, an A/D converter circuit, and a selector circuit. The pixels are electrically connected to an input terminal of the A/D converter circuit. An output terminal of the A/D converter circuit is electrically connected to one of a source and a drain of a transistor. The other of the source and the drain of the transistor is electrically connected to an input terminal of the selector circuit. The transistor includes an oxide semiconductor in an active layer. Other embodiments are described and claimed.

公开(公告)号：US09685476B2

公开(公告)日：2017-06-20

申请号：US15083755

申请日：2016-03-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Takuro Ohmaru ,  Yuki Okamoto

IPC: H01L27/146 ,  H01L29/786 ,  H01L31/0272

CPC classification number: H01L27/14643 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14665 ,  H01L29/7869 ,  H01L31/02005 ,  H01L31/022408 ,  H01L31/0272 ,  H01L31/107

Abstract: To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.

公开(公告)号：US09595964B2

公开(公告)日：2017-03-14

申请号：US14031107

申请日：2013-09-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Tatsuji Nishijima

IPC: H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K19/0008 ,  H03K19/17736 ,  H03K19/17744

Abstract: An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

Abstract translation: 目的是提供一种具有通过可编程开关彼此连接的逻辑块的可编程逻辑器件，其中可编程开关的特征在于结合在其中的氧化物半导体晶体管。 氧化物半导体晶体管的非常低的截止电流由于其保持与氧化物半导体晶体管连接的晶体管的栅极的电位的高能力而提供作为非易失性存储器的功能。 氧化物半导体晶体管用作非易失性存储器的能力允许用于控制逻辑块的连接的配置数据即使在没有电源电位的情况下也被维持。 因此，可以省略在设备启动时的配置数据的重写处理，这有助于降低设备的功耗。

公开(公告)号：US09372694B2

公开(公告)日：2016-06-21

申请号：US13796063

申请日：2013-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda

IPC: G06F7/38 ,  G06F7/00 ,  G06F9/30 ,  G06F1/32 ,  G11C5/00 ,  G06F11/14

CPC classification number: G06F9/30145 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/30141 ,  G06F11/14 ,  G11C5/00 ,  Y02D10/171 ,  Y02D50/20

Abstract: A low-power processor that does not easily malfunction is provided. Alternatively, a low-power processor having high processing speed is provided. Alternatively, a method for driving the processor is provided. In power gating, the processor performs part of data backup in parallel with arithmetic processing and performs part of data recovery in parallel with arithmetic processing. Such a driving method prevents a sharp increase in power consumption in a data backup period and a data recovery period and generation of instantaneous voltage drops and inhibits increases of the data backup period and the data recovery period.

Abstract translation: 提供了一个不容易发生故障的低功耗处理器。 或者，提供具有高处理速度的低功率处理器。 或者，提供用于驱动处理器的方法。 在电源门控中，处理器与算术处理并行执行部分数据备份，并与算术处理并行执行部分数据恢复。 这种驱动方法防止数据备份期间和数据恢复期间的功率消耗急剧增加，并且产生瞬时电压下降并且阻止数据备份周期和数据恢复期间的增加。

公开(公告)号：US09030232B2

公开(公告)日：2015-05-12

申请号：US13857185

申请日：2013-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda

IPC: H03K19/086 ,  H03K19/23 ,  H01L27/06 ,  H01L27/12

CPC classification number: H01L27/0605 ,  H01L27/0688 ,  H01L27/1203

Abstract: An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

Abstract translation: 提供了能够进行双向断电的隔离电路和包括隔离电路的半导体器件。 数据保持部分设置在隔离电路中，而不需要在隔离电路之外额外提供数据保持部分，并且要输入到此时处于断开状态的逻辑电路的数据被存储在 数据保持部。 数据保持部分可以使用具有小截止电流和缓冲器的晶体管来形成。 缓冲器可以包括逆变器电路和时钟反相器电路。

公开(公告)号：US08981367B2

公开(公告)日：2015-03-17

申请号：US13683029

申请日：2012-11-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Takuro Ohmaru

IPC: H01L29/78

CPC classification number: H01L27/1251 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/045 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor.

Abstract translation: 半导体器件包括：第一晶体管，其包括在其氧化物半导体层下方的第一栅极电极和位于其氧化物半导体层上方的第二栅电极;以及第二晶体管，其在其氧化物半导体层上方包括第一栅极电极和第二栅电极， 其氧化物半导体层被设置成至少部分地与第一晶体管重叠。 在半导体器件中，用作第一晶体管的第二栅电极的导电膜和第二晶体管的第二栅电极在第一晶体管和第二晶体管之间共用。 注意，第二栅电极不仅控制第一晶体管和第二晶体管的阈值电压（Vth），而且还具有减小从第一晶体管和第二晶体管的各个第一栅电极施加的电场的干扰的效果。

公开(公告)号：US08873308B2

公开(公告)日：2014-10-28

申请号：US13923696

申请日：2013-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Atsuo Isobe ,  Yuji Iwaki ,  Koichiro Kamata ,  Yasuyuki Takahashi ,  Masumi Nomura

IPC: G11C14/00 ,  G11C29/00 ,  G11C5/06 ,  G11C5/14 ,  G11C16/30 ,  G06F1/32 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C16/30 ,  G06F1/3203 ,  G06F1/3275 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/20 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit that consumes less power by stop of supply of power for a short time. In a storage element, before supply of power is stopped, data in a first storage circuit is stored to a second storage circuit, and the data is read from the second storage circuit and a verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. After supply of power is restarted, the data in the second storage circuit is stored to the first storage circuit, and the verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. In such a manner, verification can be performed without requiring a time for verification.

Abstract translation: 信号处理电路通过在短时间内停止供电而消耗较少的功率。 在存储元件中，在停止供电之前，将第一存储电路中的数据存储到第二存储电路，并且从第二存储电路读取数据，并且验证电路可以确定第二存储电路中的数据 存储电路与第一存储电路中的数据匹配。 在重新开始供电之后，第二存储电路中的数据被存储到第一存储电路，并且验证电路可以确定第二存储电路中的数据是否与第一存储电路中的数据匹配。 以这种方式，可以执行验证，而不需要验证时间。

公开(公告)号：US08704221B2

公开(公告)日：2014-04-22

申请号：US13716924

申请日：2012-12-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Takuro Ohmaru

IPC: H01L29/12

CPC classification number: H01L27/1255 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/1225 ,  H01L28/60

Abstract: A semiconductor device with high productivity and high yield is provided. The semiconductor device includes a word line, a capacitor line, a first bit line, a second bit line, and a first transistor and a second transistor each of which includes a gate, a source, and a drain. The first transistor and the second transistor at least partly overlap with each other, and the gates of the first transistor and the second transistor are connected to the word line. A capacitor is formed between at least part of the capacitor line and each of the drains of the first transistor and the second transistor. The first bit line is connected to the source of the first transistor, and the second bit line is connected to the source of the second transistor.

Abstract translation: 提供了高生产率和高产量的半导体器件。 半导体器件包括字线，电容线，第一位线，第二位线，以及包括栅极，源极和漏极的第一晶体管和第二晶体管。 第一晶体管和第二晶体管彼此至少部分重叠，并且第一晶体管和第二晶体管的栅极连接到字线。 电容器形成在电容器线的至少一部分与第一晶体管和第二晶体管的漏极中的每一个之间。 第一位线连接到第一晶体管的源极，第二位线连接到第二晶体管的源极。

公开(公告)号：US20130315011A1

公开(公告)日：2013-11-28

申请号：US13900140

申请日：2013-05-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuyuki Takahashi ,  Seiichi Yoneda

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C11/005

Abstract: A semiconductor device in which a nonvolatile memory can normally operate and power saving can be performed with a P-state function, and a driving method of the semiconductor device are provided. The semiconductor device includes: a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core; a first memory circuit and a second memory circuit which store state data; a second circuit generating a power supply voltage and a third circuit generating a clock which are electrically connected to the first circuit; and the processor core electrically connected to the second circuit and the third circuit through a switch. The processor cores includes: a volatile memory; and a nonvolatile memory transmitting and receiving data to/from the first memory.

Abstract translation: 可以通过P状态功能来执行其中非易失性存储器可以正常操作和省电的半导体器件，并且提供半导体器件的驱动方法。 半导体器件包括：第一电路，被配置为控制包括处理器核心的驱动电压和时钟频率的状态; 存储状态数据的第一存储器电路和第二存储器电路; 产生电源电压的第二电路和产生电连接到第一电路的时钟的第三电路; 并且处理器核心通过开关电连接到第二电路和第三电路。 处理器核心包括：易失性存储器; 以及向/从第一存储器发送和接收数据的非易失性存储器。