公开(公告)号：US09812616B2

公开(公告)日：2017-11-07

申请号：US15329993

申请日：2015-07-30

Applicant: SEOUL VIOSYS CO., LTD.

Inventor： Chi Hyun In ,  Sang Min Kim ,  Dae Seok Park ,  Eun Ji Park ,  Hong Suk Cho

IPC: H01L27/15 ,  H01L33/46 ,  H01L33/40 ,  H01L33/62 ,  H01L33/14

CPC classification number: H01L33/46 ,  H01L33/14 ,  H01L33/38 ,  H01L33/405 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/13 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/00014

Abstract: The present invention relates to a light-emitting diode having enhanced liability. More particularly, a light-emitting diode has enhanced liability in a high-temperature and/or high humidity environment as well as in a room-temperature environment and can have decrease in light-emitting characteristics prevented. In addition, the present invention relates to a light-emitting diode comprising a structure which enables enhancing of light reflection and having enhanced light extraction efficiency by means of light reflection through the structure.

公开(公告)号：US20160233386A1

公开(公告)日：2016-08-11

申请号：US15132887

申请日：2016-04-19

Applicant: Seoul Viosys Co., Ltd.

Inventor： Jong Hyeon Chae ,  Jong Min Jang ,  Won Young Roh ,  Daewoong Suh ,  Dae Sung Cho ,  Joon Sup Lee ,  Kyu Ho Lee ,  Chi Hyun In

IPC: H01L33/40 ,  H01L33/46 ,  H01L33/42 ,  H01L33/20 ,  H01L33/32 ,  H01L33/12

CPC classification number: H01L33/405 ,  H01L33/0075 ,  H01L33/08 ,  H01L33/12 ,  H01L33/14 ,  H01L33/20 ,  H01L33/22 ,  H01L33/32 ,  H01L33/38 ,  H01L33/42 ,  H01L33/44 ,  H01L33/46 ,  H01L33/486 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0058

Abstract: A light emitting diode includes a first conductive type semiconductor layer and a mesa disposed on the first conductive type semiconductor layer. The mesa includes an active layer and a second conductive type semiconductor layer. A reflective electrode is disposed on the mesa to be in ohmic-contact with the second conductive type semiconductor layer. A current spreading layer is disposed on the mesa and the reflective electrode. A first portion of the current spreading layer is in ohmic-contact with an upper surface of an end portion of the first conductive type semiconductor layer. A lower insulating layer is disposed between the mesa and the current spreading layer, and the reflective electrode and the current spreading layer. An upper insulating layer covers the current spreading layer and includes a first hole exposing a second portion of the current spreading layer that is disposed on an upper portion of the mesa.

Abstract translation: 发光二极管包括设置在第一导电类型半导体层上的第一导电类型半导体层和台面。 台面包括有源层和第二导电类型半导体层。 反射电极设置在台面上以与第二导电类型半导体层欧姆接触。 电流扩散层设置在台面和反射电极上。 电流扩散层的第一部分与第一导电类型半导体层的端部的上表面欧姆接触。 下部绝缘层设置在台面与电流扩散层之间，反射电极和电流扩展层之间。 上绝缘层覆盖电流扩展层，并且包括暴露设置在台面上部的电流扩展层的第二部分的第一孔。

公开(公告)号：US09356191B2

公开(公告)日：2016-05-31

申请号：US14726031

申请日：2015-05-29

Applicant: SEOUL VIOSYS CO., LTD.

Inventor： Jong Min Jang ,  Kyu Ho Lee ,  Chang Suk Han ,  Hwa Mok Kim ,  Daewoong Suh ,  Chi Hyun In ,  Jong Hyeon Chae

IPC: H01L33/22 ,  H01L21/02 ,  H01L29/06 ,  H01L33/00 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L33/22 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/0657 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32

Abstract: An epitaxial wafer includes a growth substrate, a mask pattern disposed on the growth substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern and including a first void disposed on the masking region. The first void includes a lower void disposed between a lower surface of the epitaxial layer and the masking region, and an upper void extending from the lower void into the epitaxial layer, the lower void having a greater width than the upper void.

Abstract translation: 外延晶片包括生长衬底，设置在生长衬底上并包括掩模区域和开口区域的掩模图案，以及覆盖掩模图案并且包括设置在掩蔽区域上的第一空隙的外延层。 第一空隙包括设置在外延层的下表面和掩蔽区域之间的下部空隙和从下部空隙延伸到外延层中的上部空隙，下部空隙具有比上部空隙更大的宽度。

公开(公告)号：US09218967B2

公开(公告)日：2015-12-22

申请号：US14361117

申请日：2012-11-27

Applicant: Seoul Viosys Co., Ltd.

Inventor： Daewoong Suh ,  Kyu Ho Lee ,  Jong Min Jang ,  Chi Hyun In

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/02 ,  H01L33/00

CPC classification number: H01L21/02664 ,  H01L21/0254 ,  H01L21/02587 ,  H01L33/0079

Abstract: The present invention provides a method for separating an epitaxial layer from a growth substrate, comprising growing an epitaxial layer including a plurality of layers on a growth substrate; etching an edge of at least one layer in the epitaxial layer to form a notch; forming a bonding layer on the epitaxial layer, contacting a bonding substrate onto the bonding layer, and then heating the bonding layer to a bonding temperature for joining the epitaxial layer and the bonding substrate; and cooling the bonding layer after the heating of the boding layer, so that the epitaxial layer and the bonding substrate are joined by the bonding layer, and the epitaxial layer is separated from the growth substrate, wherein the separating the epitaxial layer from the growth substrate starts with separation from the at least one layer where the notch is formed.

Abstract translation: 本发明提供了一种用于从生长衬底分离外延层的方法，包括在生长衬底上生长包括多个层的外延层; 蚀刻外延层中的至少一层的边缘以形成凹口; 在所述外延层上形成接合层，将接合基板接触到所述接合层上，然后将所述接合层加热至接合所述外延层和所述接合基板的接合温度; 并且在加热所述粘合层之后冷却所述接合层，使得所述外延层和所述接合基板通过所述接合层接合，并且所述外延层与所述生长基板分离，其中所述外延层与所述生长基板分离 从形成有凹口的至少一个层分离开始。

公开(公告)号：US20150200334A1

公开(公告)日：2015-07-16

申请号：US14671491

申请日：2015-03-27

Applicant: Seoul Viosys Co., Ltd.

Inventor： Jong Hyeon Chae ,  Jong Min Jang ,  Won Young Roh ,  Daewoong Suh ,  Dae Sung Cho ,  Joon Sup Lee ,  Kyu Ho Lee ,  Chi Hyun In

IPC: H01L33/46 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01L33/42 ,  H01L33/20

CPC classification number: H01L33/405 ,  H01L33/0075 ,  H01L33/08 ,  H01L33/12 ,  H01L33/14 ,  H01L33/20 ,  H01L33/22 ,  H01L33/32 ,  H01L33/38 ,  H01L33/42 ,  H01L33/44 ,  H01L33/46 ,  H01L33/486 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0058

Abstract: A light-emitting diode including a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer and having a conductivity type different than that of the first semiconductor layer, and a reflective pattern disposed on the second semiconductor layer and configured to reflect light emitted from the active layer, the reflective pattern having heterogeneous metal layers and configured to absorb stress caused by differences in coefficient of thermal expansion between the heterogeneous metal layers.

Abstract translation: 一种发光二极管，包括基板，设置在基板上的第一半导体层，设置在第一半导体层上的有源层，设置在有源层上并具有与第一半导体层不同的导电类型的第二半导体层 以及设置在所述第二半导体层上并且被配置为反射从所述有源层发射的光的反射图案，所述反射图案具有异质金属层并且被配置为吸收由所述异质金属层之间的热膨胀系数的差异引起的应力。

公开(公告)号：US20140179043A1

公开(公告)日：2014-06-26

申请号：US14138923

申请日：2013-12-23

Applicant: Seoul Viosys Co., Ltd.

Inventor： Jong Min Jang ,  Hwa Mok Kim ,  Kyu Ho Lee ,  Chang Hoon Kim ,  Daewoong Suh ,  Chi Hyun In ,  Dae Seok Park ,  Jong Hyeon Chae

IPC: H01L33/00

CPC classification number: H01L33/0079 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/0095 ,  H01L33/22

Abstract: A method of fabricating a semiconductor device, the method including: forming a first mask pattern including a masking region and an open region on a substrate; forming a sacrificial layer to cover the substrate and the first mask pattern; patterning the sacrificial layer to form a seed layer and to expose the first mask pattern; forming a second mask pattern on the exposed first mask pattern; forming an epitaxial layer on the seed layer and the second mask pattern, and forming a void between the second mask pattern and the epitaxial layer; and separating the substrate from the epitaxial layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括：在衬底上形成包括掩模区域和开放区域的第一掩模图案; 形成覆盖衬底和第一掩模图案的牺牲层; 图案化所述牺牲层以形成种子层并暴露所述第一掩模图案; 在所述暴露的第一掩模图案上形成第二掩模图案; 在种子层和第二掩模图案上形成外延层，并在第二掩模图案和外延层之间形成空隙; 以及将衬底与外延层分离。