公开(公告)号：US11652088B2

公开(公告)日：2023-05-16

申请号：US17452824

申请日：2021-10-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  SungSoo Kim ,  HeeSoo Lee

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L23/538 ,  H01L23/552 ,  H01L24/11 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/1134 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/03

Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

公开(公告)号：US11189598B2

公开(公告)日：2021-11-30

申请号：US16570165

申请日：2019-09-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  SungSoo Kim ,  HeeSoo Lee

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

公开(公告)号：US20210151386A1

公开(公告)日：2021-05-20

申请号：US17163776

申请日：2021-02-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee ,  Wanil Lee ,  SangDuk Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66

Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.

公开(公告)号：US20200219835A1

公开(公告)日：2020-07-09

申请号：US16821093

申请日：2020-03-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  OhHan Kim ,  HeeSoo Lee ,  DaeHyeok Ha ,  Wanil Lee

IPC: H01L23/00 ,  H01L23/538

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.

公开(公告)号：US20180294236A1

公开(公告)日：2018-10-11

申请号：US16005387

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US20180294235A1

公开(公告)日：2018-10-11

申请号：US16005348

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US09997468B2

公开(公告)日：2018-06-12

申请号：US15091049

申请日：2016-04-05

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/01029 ,  H01L2224/81

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.