公开(公告)号：US20160173171A1

公开(公告)日：2016-06-16

申请号：US14849385

申请日：2015-09-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: H04B5/00 ,  H02H9/04

CPC classification number: H04B5/0037 ,  G06K19/07769 ,  H02H9/044

Abstract: An electronic device includes at least one processing circuit connected through at least one terminal at a first reference voltage. At least one radio frequency communication circuit is connected at least to receive the reference voltage. At least one first pad is intended to be taken to a second reference voltage of at least one electronic circuit external to the device. At least one first resistive impedance is coupled between the terminal and the first pad.

Abstract translation: 电子设备包括至少一个处理电路，其通过至少一个终端以第一参考电压连接。 至少一个射频通信电路至少连接以接收参考电压。 至少一个第一焊盘旨在被带到设备外部的至少一个电子电路的第二参考电压。 至少一个第一电阻阻抗耦合在端子和第一焊盘之间。

公开(公告)号：US09245627B2

公开(公告)日：2016-01-26

申请号：US14296014

申请日：2014-06-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00 ,  G11C16/04 ,  G11C5/02 ,  G11C16/20 ,  G11C11/404

CPC classification number: G11C16/0408 ,  G11C11/404 ,  G11C14/0018 ,  G11C14/0063 ,  G11C16/20

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract translation: 存储器件包括具有基本SRAM型单元的存储单元和耦合在供电端和基本SRAM型单元之间的基本模块。 基本模块具有包括浮栅晶体管的单个非易失性EEPROM单元存储单元。 基本模块还具有可控制的互连级，其可以由存储器单元外部的控制信号控制。 非易失性基本存储单元和可控互连级彼此连接。 当存储在基本SRAM型单元中的数据项被编程到非易失性单元中时，非易失性存储单元的浮置栅晶体管被控制为截止。

公开(公告)号：US20150117116A1

公开(公告)日：2015-04-30

申请号：US14511661

申请日：2014-10-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/26 ,  G11C16/10

CPC classification number: G11C16/102 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3481 ,  G11C16/3495 ,  G11C2211/5622 ,  G11C2211/5624 ,  G11C2211/5632

Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.

Abstract translation: 在对单元进行编程的阶段期间，将第一电压施加到源区，并且将高于第一电压的第二电压施加到漏区，直到电池进入导通。 要写入的数据项的数值由施加到控制栅极的控制电压的电平控制，并且数据项实际上用单元格导通时的数值写入。 然后程序停止。

公开(公告)号：US08630073B2

公开(公告)日：2014-01-14

申请号：US13838422

申请日：2013-03-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H02H9/00

CPC classification number: H01L27/0248 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.

Abstract translation: 一种防止静电放电的集成电路，具有耦合到放大级的输出焊盘，每个级在第一和第二电源轨之间包括与N沟道MOS功率晶体管串联的P沟道MOS功率晶体管，该集成电路进一步 包括当在第一和第二电源轨之间发生正的过电压时同时接通两个晶体管的保护电路。

公开(公告)号：US20130242442A1

公开(公告)日：2013-09-19

申请号：US13838422

申请日：2013-03-15

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François Tailliet

IPC: H01L27/02

CPC classification number: H01L27/0248 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.

Abstract translation: 一种防止静电放电的集成电路，具有耦合到放大级的输出焊盘，每个级在第一和第二电源轨之间包括与N沟道MOS功率晶体管串联的P沟道MOS功率晶体管，该集成电路进一步 包括当在第一和第二电源轨之间发生正的过电压时同时接通两个晶体管的保护电路。

公开(公告)号：US11892958B2

公开(公告)日：2024-02-06

申请号：US17667515

申请日：2022-02-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G06F13/16 ,  G06F12/02

CPC classification number: G06F13/1668 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2213/0016

Abstract: The present description concerns attribution, on a communication over an I2C bus, of a first address to a first device by a second device, wherein the second device sends the first address over the I2C bus and, if the second device receives no acknowledgment data, then the first device records the first address.

公开(公告)号：US11817149B2

公开(公告)日：2023-11-14

申请号：US17930250

申请日：2022-09-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C14/00

CPC classification number: G11C14/0063

Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.

公开(公告)号：US11696438B2

公开(公告)日：2023-07-04

申请号：US16928465

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L21/00 ,  H10B41/00 ,  H01L29/423 ,  G11C7/18 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  G11C16/08 ,  G11C16/24 ,  H10B41/35 ,  H01L29/788

CPC classification number: H10B41/00 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66825 ,  H10B41/35 ,  H01L29/7881

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US11670385B2

公开(公告)日：2023-06-06

申请号：US17558123

申请日：2021-12-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G11C16/32 ,  G11C16/10

CPC classification number: G11C16/32 ,  G11C16/10

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

公开(公告)号：US11386963B2

公开(公告)日：2022-07-12

申请号：US17166107

申请日：2021-02-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.