公开(公告)号：US20240194273A1

公开(公告)日：2024-06-13

申请号：US18239480

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chiweon Yoon ,  Chihyun Kim ,  Philkyu Kang ,  Junehong Park ,  Jayang Yoon ,  Hyeongdo Choi

IPC: G11C16/30 ,  G06F1/20 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/30 ,  G06F1/206 ,  G11C16/0483 ,  G11C16/08

Abstract: A nonvolatile memory device comprising a charge pump circuit with pump units connected in series that receives an external voltage for charge pumping and outputs a pump voltage in stages according to stage control signals, a switching circuit that controls the charge pump circuit to output pumping voltages in response to switch control signals, a stage controller that outputs the stage control signals and the switch control signals based on a temperature code, and a digital temperature sensor that generates the temperature code.

公开(公告)号：US11984170B2

公开(公告)日：2024-05-14

申请号：US18160620

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon

IPC: G11C16/32 ,  G11C16/04 ,  H01L25/065

CPC classification number: G11C16/32 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06506

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

公开(公告)号：US11783874B2

公开(公告)日：2023-10-10

申请号：US17470579

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeon Park ,  Byunghoon Jeong ,  Chiweon Yoon

IPC: G11C7/10 ,  G11C8/06 ,  G11C7/20

CPC classification number: G11C7/1012 ,  G11C7/109 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/1084 ,  G11C7/20 ,  G11C8/06

Abstract: A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.

公开(公告)号：US20230146885A1

公开(公告)日：2023-05-11

申请号：US17863037

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4099 ,  G11C11/4074 ,  G11C11/4085

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US10236065B2

公开(公告)日：2019-03-19

申请号：US16049863

申请日：2018-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C11/00 ,  G11C16/08 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

公开(公告)号：US12210773B2

公开(公告)日：2025-01-28

申请号：US17528285

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Seonkyoo Lee ,  Byunghoon Jeong

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K19/00 ,  H10B43/27

Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.

公开(公告)号：US12073917B2

公开(公告)日：2024-08-27

申请号：US17404510

申请日：2021-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Manjae Yang ,  Chiweon Yoon ,  Junha Lee ,  Byunghoon Jeong

IPC: G06F1/04 ,  G06F3/06 ,  G11C7/22 ,  G11C29/02 ,  G11C5/14

CPC classification number: G11C7/222 ,  G06F1/04 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C29/023 ,  G11C29/028 ,  G11C5/145

Abstract: A storage device includes a plurality of memory chips and a chip. The plurality of memory chips includes a first memory chip configured to generate a first signal based on a first clock signal, and a second memory chip configured to generate a second signal based on a second clock signal. The chip is configured to receive the first and second signals and generate and output a first and second comparison signal based on a duty cycle of the first and second signals. The first memory chip is further configured to generate a first corrected signal by adjusting a duty cycle of the first clock signal based on the first comparison signal, and the second memory chip is further configured to generate a second corrected signal by adjusting a duty cycle of the second clock signal based on the second comparison signal.

公开(公告)号：US11810638B2

公开(公告)日：2023-11-07

申请号：US17410210

申请日：2021-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonkyoo Lee ,  Chiweon Yoon ,  Byunghoon Jeong ,  Youngmin Jo

IPC: G11C7/10 ,  H01L25/065 ,  G06F13/42

CPC classification number: G11C7/1048 ,  H01L25/0657 ,  G06F13/4282 ,  G11C2207/12 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

公开(公告)号：US20230307068A1

公开(公告)日：2023-09-28

申请号：US18184842

申请日：2023-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjae LEE ,  Byungjoon Yoo ,  Chiweon Yoon ,  Cheonan Lee

IPC: G11C16/30 ,  H02M3/07 ,  G11C16/32

CPC classification number: G11C16/30 ,  H02M3/07 ,  G11C16/32

Abstract: A memory device includes a memory cell array region electrically connected to a plurality of word lines and a plurality of bit lines and the memory cell array including a plurality of memory cells, and a peripheral circuit region under the memory cell array region, wherein the memory cell array region and the peripheral circuit region are electrically connected by through vias, the peripheral circuit region includes a voltage generator configured to generate an operating voltage to apply to the word lines, the voltage generator includes a pumping capacitor unit configured to charge and pump a voltage based on a clock signal, and a signal controller configured to control the clock signal and a current flowing through the pumping capacitor unit, the signal controller includes a clock driver configured to apply a clock signal to the pumping capacitor, and the signal controller is adjacent to the through vias.

公开(公告)号：US11756592B2

公开(公告)日：2023-09-12

申请号：US17477931

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Byunghoon Jeong ,  Tongsung Kim ,  Chiweon Yoon ,  Seonkyoo Lee

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/109 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/1084

Abstract: A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.