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    Integrated circuit and storage device including integrated circuit
    32.
    发明授权
    Integrated circuit and storage device including integrated circuit 有权

    公开(公告)号：US09897650B2

    公开(公告)日：2018-02-20

    申请号：US14957987

    申请日：2015-12-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Na ,  ChaeHoon Kim ,  HyunJin Kim ,  Jangwoo Lee ,  Jeongdon Ihm

    IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

    CPC classification number: G01R31/31716 ,  G01R31/2884 ,  G01R31/3177

    Abstract: An integrated circuit including first pads and second pads, a first receiver circuit and a first driver circuit respectively connected to the first pad, a second receiver circuit and a second driver circuit respectively connected to the second pad, and a first loopback circuit having a first input terminal electrically connected to the first receiver circuit, a first output terminal electrically connected to the first driver circuit, a second output terminal electrically connected to the second driver circuit, and a second input terminal electrically connected to the second receiver circuit may be provided. At a normal mode, the first loopback circuit electrically connects the first input terminal to the second output terminal and electrically connects the second input terminal to the first output terminal. At a test mode, the first loopback circuit electrically connects the first input terminal to the first output terminal.

    INTEGRATED CIRCUIT AND STORAGE DEVICE INCLUDING THE SAME
    34.
    发明申请
    INTEGRATED CIRCUIT AND STORAGE DEVICE INCLUDING THE SAME 有权
    集成电路和存储设备，包括它们

    公开(公告)号：US20160204782A1

    公开(公告)日：2016-07-14

    申请号：US14960748

    申请日：2015-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JANGWOO LEE ,  HyunJin Kim ,  Daehoon Na ,  Jeongdon Ihm

    IPC: H03K19/0175 ,  G11C7/10

    CPC classification number: H03K19/017545 ,  G11C7/04 ,  G11C7/1069 ,  G11C7/1096 ,  G11C16/0483 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/108

    Abstract: An integrated circuit includes an input/output pad, a driver circuit connected to the input/output pad, and a receiver circuit connected to the input/output pad, and a code generator. The driver circuit is configured to output an output signal to an external device through the input/output pad. The receiver circuit is configured to receive an input signal from the external device through the input/output pad. The code generator is configured to generate a termination code of the external device in response to a signal output from the receiver circuit.

    Abstract translation: 集成电路包括输入/​​输出焊盘，连接到输入/输出焊盘的驱动器电路以及连接到输入/输出焊盘的接收器电路和代码发生器。 驱动电路被配置为通过输入/输出板将输出信号输出到外部设备。 接收器电路被配置为通过输入/输出接收器从外部设备接收输入信号。 代码生成器被配置为响应于从接收器电路输出的信号来产生外部设备的终止代码。

    Memory systems including an input/output buffer circuit
    35.
    发明授权
    Memory systems including an input/output buffer circuit 有权
    存储器系统包括一个输入/输出缓冲电路

    公开(公告)号：US09263105B2

    公开(公告)日：2016-02-16

    申请号：US14143154

    申请日：2013-12-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

    IPC: G11C7/10 ,  G11C7/22 ,  G11C7/04

    CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

    Abstract: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

    Abstract translation: 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控​​制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。

    MEMORY DEVICE AND MEMORY SYSTEM
    36.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20250061939A1

    公开(公告)日：2025-02-20

    申请号：US18806022

    申请日：2024-08-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

    IPC: G11C11/4096 ,  G11C11/408

    Abstract: A memory device includes at least one bank including a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may store normal data and may be connected to a plurality of first wordlines, the second sub-bank may store metadata corresponding to the normal data and may be connected to a plurality of second wordlines, and metadata for normal data corresponding to each of the first wordlines may be stored in each of second wordlines, respectively corresponding to the first wordlines.

    Interface circuit, memory device, storage device, and method of operating the memory device
    40.
    发明授权
    Interface circuit, memory device, storage device, and method of operating the memory device 有权

    公开(公告)号：US11960728B2

    公开(公告)日：2024-04-16

    申请号：US17536506

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Na ,  Jangwoo Lee ,  Jeongdon Ihm

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

    Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

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