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111 条记录 (耗时 0.028 秒)

    Formation of a MOSFET using an angled implant
    31.
    发明授权
    Formation of a MOSFET using an angled implant 有权
    使用成角度的植入物形成MOSFET

    公开(公告)号：US07772075B2

    公开(公告)日：2010-08-10

    申请号：US12509935

    申请日：2009-07-27

    申请人： Sameer Pendharkar ,  Binghua Hu

    发明人： Sameer Pendharkar ,  Binghua Hu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

    摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

    摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

    METHOD OF FORMING SEMICONDUCTOR WELLS
    32.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR WELLS 有权
    形成半导体阱的方法

    公开(公告)号：US20100148125A1

    公开(公告)日：2010-06-17

    申请号：US12335756

    申请日：2008-12-16

    申请人： Seetharaman Sridar ,  Marie Denison ,  Sameer Pendharkar

    发明人： Seetharaman Sridar ,  Marie Denison ,  Sameer Pendharkar

    IPC分类号： H01B1/02 ,  H01L21/425

    CPC分类号： H01L21/2652

    摘要： A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.

    摘要翻译： 提供形成半导体器件的方法。 提供具有形成在其上的电介质层的衬底。 电介质层覆盖衬底的受保护区域，并且具有暴露衬底的第一未受保护区域的第一开口。 第一掺杂剂通过电介质层中的第一开口注入第一未保护区域，并通过电介质层注入保护区域。

    Laterally diffused MOSFET
    33.
    发明授权
    Laterally diffused MOSFET 有权
    横向MOSFET扩散

    公开(公告)号：US07732863B2

    公开(公告)日：2010-06-08

    申请号：US12120158

    申请日：2008-05-13

    申请人： Sameer Pendharkar ,  Binghua Hu

    发明人： Sameer Pendharkar ,  Binghua Hu

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66712 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7809 ,  H01L29/7816

    摘要： A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.

    摘要翻译： 一种LDMOS晶体管，其具有位于n型区域的外边界和p体区域的内边界之间的沟道区域。 LDMOS通道区域的宽度小于n +型区域的外边界与p体区域的内边界之间的距离的80％。 此外，制造LDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。 此外，VDMOS具有位于第一和第二p体区域的内边界和第一和第二p体区域的n型区域的外边界之间的第一和第二沟道区域。 VDMOS的第一和第二沟道区域的宽度小于第一和第二p体区域的内边界与第一和第二p体区域的n +型区域的外边界之间的距离的80％ 身体区域。 此外，制造VDMOS晶体管的方法，其中n型掺杂剂以大于用于注入p型掺杂剂的角度的角度注入。

    Robust DEMOS transistors and method for making the same
    34.
    发明授权
    Robust DEMOS transistors and method for making the same 有权
    坚固的DEMOS晶体管及其制造方法

    公开(公告)号：US07514329B2

    公开(公告)日：2009-04-07

    申请号：US11325165

    申请日：2006-01-04

    申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

    发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

    摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

    摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

    System for high-precision double-diffused MOS transistors
    37.
    发明申请
    System for high-precision double-diffused MOS transistors 审中-公开
    高精度双扩散MOS晶体管系统

    公开(公告)号：US20050127409A1

    公开(公告)日：2005-06-16

    申请号：US11042536

    申请日：2005-01-25

    申请人： Henry Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    发明人： Henry Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L21/336 ,  H01L31/062

    CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7801

    摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.

    摘要翻译： 本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。 本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。 本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。 在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。

    System for high-precision double-diffused MOS transistors
    38.
    发明授权
    System for high-precision double-diffused MOS transistors 有权
    高精度双扩散MOS晶体管系统

    公开(公告)号：US06867100B2

    公开(公告)日：2005-03-15

    申请号：US10326214

    申请日：2002-12-19

    申请人： Henry L. Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    发明人： Henry L. Edwards ,  Sameer Pendharkar ,  Joe Trogolo ,  Tathagata Chatterjee ,  Taylor Efland

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7801

    摘要： The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.

    摘要翻译： 本发明提供了一种用于有效地生产多功能，高精度的MOS器件结构的系统，其中直线区域主导器件的行为，以简单，高效和成本有效的方式提供精确匹配大型器件的最小几何器件。 本发明提供了用于生产双扩散半导体器件的方法和装置，其最小化端帽区域的性能影响。 本发明提供一种MOS结构，其具有护城河区域（404,516,616）和与护城河区域重叠的氧化物区域（414,512,608）。 在氧化物区域内形成双扩散区域（402,504,618），具有端盖区域（406,502,620），其可以利用几何和植入操作被有效地去激活。