STRUCTURE FOR IMPROVING DIE SAW QUALITY
    31.
    发明申请
    STRUCTURE FOR IMPROVING DIE SAW QUALITY 有权
    改善牙齿质量的结构

    公开(公告)号:US20100252916A1

    公开(公告)日:2010-10-07

    申请号:US12417394

    申请日:2009-04-02

    IPC分类号: H01L23/544

    摘要: A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.

    摘要翻译: 提供了一种半导体器件,其包括半导体衬底,形成在半导体衬底上的多个管芯,所述多个管芯沿着第一方向延伸的第一区域彼此分离,并且沿着不同于第二方向的第二方向延伸的第二区域 第一方向,形成在第三区域内的虚设金属结构,所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域,形成在所述基板上的多个金属互连层,以及形成在所述第二区域上的多个电介质层 基质。 每个金属互连层设置在每个介电层内,并且至少一个电介质层的介电常数小于约2.6。

    WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY
    34.
    发明申请
    WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY 有权
    用于提高IC可靠性的WAFER SCRIBE LINE结构

    公开(公告)号:US20090140393A1

    公开(公告)日:2009-06-04

    申请号:US12054082

    申请日:2008-03-24

    IPC分类号: H01L23/58

    摘要: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.

    摘要翻译: 公开了具有多层布线结构的半导体晶片。 晶片包括排列在晶片上的多个芯片管芯区域和在芯片管芯区域之间的划线区域。 具有在ELK布线层之上的USG顶层布线层的半导体晶片的划线具有至少一个金属膜结构,其基本上覆盖两个划线相交的拐角区域,以在晶片切割操作期间在USG / ELK界面处抑制分层。

    SEMICONDUCTOR TEST PAD STRUCTURES
    37.
    发明申请

    公开(公告)号:US20110287627A1

    公开(公告)日:2011-11-24

    申请号:US13197003

    申请日:2011-08-03

    IPC分类号: H01L21/768

    摘要: A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.

    摘要翻译: 具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。 互连结构包括多个堆叠的金属层,每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。 在一个实施例中,至少一个金属通孔条被嵌入到互连结构中,并将金属层中的每个测试焊盘电连接在一起。 在一些实施例中,通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。 在其它实施例中,可以提供一对相对的通孔条,其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

    Semiconductor test pad structures
    38.
    发明授权
    Semiconductor test pad structures 有权
    半导体测试板结构

    公开(公告)号:US08013333B2

    公开(公告)日:2011-09-06

    申请号:US12267021

    申请日:2008-11-07

    IPC分类号: H01L23/58

    摘要: A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.

    摘要翻译: 具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。 互连结构包括多个堆叠的金属层,每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。 在一个实施例中,至少一个金属通孔条被嵌入到互连结构中,并将金属层中的每个测试焊盘电连接在一起。 在一些实施例中,通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。 在其他实施例中,可以提供一对相对的通孔条,其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

    Backend interconnect scheme with middle dielectric layer having improved strength
    39.
    发明授权
    Backend interconnect scheme with middle dielectric layer having improved strength 有权
    具有中等介电层的后端互连方案具有改进的强度

    公开(公告)号:US07936067B2

    公开(公告)日:2011-05-03

    申请号:US12121541

    申请日:2008-05-15

    IPC分类号: H01L23/48 H01L23/52 H01L29/40

    摘要: An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.

    摘要翻译: 集成电路结构包括第一,第二和第三金属化层。 第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。 第二金属化层在第一金属化层之上,并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。 第三金属化层在第二金属化层之上,并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。 集成电路结构还包括在第三金属化层上的底部钝化层。

    Seal ring structure with improved cracking protection and reduced problems
    40.
    发明授权
    Seal ring structure with improved cracking protection and reduced problems 有权
    密封环结构具有改进的开裂保护和减少的问题

    公开(公告)号:US08643147B2

    公开(公告)日:2014-02-04

    申请号:US11933931

    申请日:2007-11-01

    IPC分类号: H01L23/544

    摘要: An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

    摘要翻译: 集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。 密封环包括在上介电层中的上金属线; 连续的通孔条,其下面并邻接上部金属线,其中所述连续通孔条具有大于所述上部金属线宽度的约70%的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。 通孔棒具有基本上小于下金属线宽度的一半的宽度。