公开(公告)号：US20050258443A1

公开(公告)日：2005-11-24

申请号：US11121070

申请日：2005-05-04

申请人： Shunpei Yamazaki ,  Hideto Ohnuma ,  Aya Anzai ,  Masayuki Sakakura ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Hideto Ohnuma ,  Aya Anzai ,  Masayuki Sakakura ,  Hiromichi Godo

IPC分类号： H01L27/15 ,  H01L27/32 ,  H01L33/00 ,  H05B33/12

CPC分类号： H01L27/3244 ,  H01L27/3248 ,  H01L27/3258 ,  H01L51/5262

摘要： An object of the invention is to provide a light emitting device in which the variation in emission spectrum depending on an angle for seeing a surface through which light is emitted is reduced. The light emitting device of the invention includes a first insulating layer formed over a substrate, a second insulating layer formed over the first insulating layer, and a semiconductor layer formed over the second insulating layer. A gate insulating layer is formed to cover the second insulating layer and the semiconductor layer. A gate electrode is formed over the gate insulating layer. A first interlayer insulating layer is formed to cover the gate insulating layer and the gate electrode. An opening is formed through the first interlayer insulating layer, the gate insulating layer and the second insulating layer. A second interlayer insulating layer is formed to cover the first insulating layer and the opening. A light emitting element is formed over the opening.

摘要翻译： 本发明的一个目的是提供一种发光装置，其中发光光谱的变化取决于用于观察发射光的表面的角度。 本发明的发光器件包括形成在衬底上的第一绝缘层，形成在第一绝缘层上的第二绝缘层，以及形成在第二绝缘层上的半导体层。 形成栅极绝缘层以覆盖第二绝缘层和半导体层。 在栅绝缘层上形成栅电极。 形成第一层间绝缘层以覆盖栅极绝缘层和栅电极。 通过第一层间绝缘层，栅极绝缘层和第二绝缘层形成开口。 形成第二层间绝缘层以覆盖第一绝缘层和开口。 在开口上形成发光元件。

公开(公告)号：US20050255617A1

公开(公告)日：2005-11-17

申请号：US11121073

申请日：2005-05-04

申请人： Shunpei Yamazaki ,  Hideto Ohnuma ,  Mitsuaki Osame ,  Aya Anzai ,  Hiromichi Godo ,  Tomoya Futamura

发明人： Shunpei Yamazaki ,  Hideto Ohnuma ,  Mitsuaki Osame ,  Aya Anzai ,  Hiromichi Godo ,  Tomoya Futamura

IPC分类号： H01J1/62 ,  H01J63/04 ,  H01L21/00 ,  H01L21/77 ,  H01L27/32 ,  H01L51/52 ,  H05B33/10

CPC分类号： H01L51/5262 ,  H01L27/1248 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3258

摘要： In a method for manufacturing a display device having a light emitting element, a first base insulating film, a second base insulating film, a semiconductor layer, and a gate insulating film are formed in this order over a substrate. A gate electrode is formed over the gate insulating film to overlap with at least a part of the semiconductor layer, and a portion to be a pixel portion of the gate insulating film and the second base insulating film is doped with at least one conductive type impurities. An opening portion is formed by selectively etching the gate insulating film and second base insulating film that are each doped with impurities. The first base insulating film is exposed in a bottom face of the opening portion. Subsequently, an insulating film is formed to cover the opening portion, the gate insulating film, and the gate electrode, and a light emitting element is formed over the insulating film to overlap with at least a part of the opening portion.

摘要翻译： 在具有发光元件的显示装置的制造方法中，在衬底上依次形成第一基底绝缘膜，第二基底绝缘膜，半导体层和栅极绝缘膜。 栅极电极形成在栅极绝缘膜上方以与半导体层的至少一部分重叠，栅极绝缘膜和第二基底绝缘膜的像素部分的一部分被掺杂有至少一种导电类型的杂质 。 通过选择性地蚀刻各自掺杂有杂质的栅极绝缘膜和第二基底绝缘膜来形成开口部。 第一基底绝缘膜在开口部的底面露出。 随后，形成绝缘膜以覆盖开口部分，栅极绝缘膜和栅电极，并且在绝缘膜上形成发光元件以与开口部分的至少一部分重叠。

公开(公告)号：US08809870B2

公开(公告)日：2014-08-19

申请号：US13354617

申请日：2012-01-20

申请人： Shunpei Yamazaki ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Hiromichi Godo

IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  G11C11/403

CPC分类号： H01L29/78 ,  G11C11/403 ,  H01L27/0688 ,  H01L27/10873 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/60 ,  H01L29/7833

摘要： A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. Another problem is that an increase in memory capacity leads to an increase in the area, despite an attempt at integration through advancement of transistor miniaturization. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. In addition, a plurality of memory elements each including the transistor having a trench structure and including an oxide semiconductor is stacked in a semiconductor device, whereby the circuit area of the semiconductor device can be reduced.

摘要翻译： 需要以几十毫秒的间隔刷新常规DRAM以保存数据，这导致大的功耗。 此外，其中的晶体管经常被打开和关闭; 因此，晶体管的劣化也是一个问题。 随着存储容量的增加和晶体管小型化的发展，这些问题变得越来越重要。 另一个问题是，尽管通过推进晶体管小型化来尝试集成，但是存储容量的增加导致了面积的增加。 提供了一种晶体管，其包括氧化物半导体并且具有包括用于栅电极的沟槽和用于元件隔离的沟槽的沟槽结构。 此外，在半导体器件中堆叠包括具有沟槽结构并且包括氧化物半导体的晶体管的多个存储元件，由此可以减小半导体器件的电路面积。

公开(公告)号：US08704216B2

公开(公告)日：2014-04-22

申请号：US12706737

申请日：2010-02-17

申请人： Hiromichi Godo ,  Kengo Akimoto ,  Shunpei Yamazaki

发明人： Hiromichi Godo ,  Kengo Akimoto ,  Shunpei Yamazaki

IPC分类号： H01L29/786

CPC分类号： H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.

摘要翻译： 目的是为了减小阈值电压的变化，以稳定每个使用氧化物半导体层的薄膜晶体管的电特性。 目的是减少关断电流。 使用氧化物半导体层的薄膜晶体管通过在氧化物半导体层上层叠含有绝缘氧化物的氧化物半导体层而形成，使得氧化物半导体层和源极和漏极电极层彼此接触，氧化物半导体层包含绝缘体 介于其间的氧化物; 从而可以减小薄膜晶体管的阈值电压的变化，从而能够稳定电特性。 此外，可以减少截止电流。

公开(公告)号：US08373203B2

公开(公告)日：2013-02-12

申请号：US12954222

申请日：2010-11-24

申请人： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

发明人： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC分类号： H01L27/148

CPC分类号： H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm an inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

摘要翻译： 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，氧化物半导体层和栅极绝缘层的厚度为15nm〜30nm，包括20nm〜50nm ，或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

公开(公告)号：US08305109B2

公开(公告)日：2012-11-06

申请号：US12880312

申请日：2010-09-13

申请人： Kenichi Okazaki ,  Yoshiaki Oikawa ,  Hotaka Maruyama ,  Hiromichi Godo ,  Shunpei Yamazaki

发明人： Kenichi Okazaki ,  Yoshiaki Oikawa ,  Hotaka Maruyama ,  Hiromichi Godo ,  Shunpei Yamazaki

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H01L27/1233 ,  H01L27/0207 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288

摘要： An object is to obtain a desired threshold voltage of a thin film transistor using an oxide semiconductor. Another object is to suppress a change of the threshold voltage over time. Specifically, an object is to apply the thin film transistor to a logic circuit formed using a transistor having a desired threshold voltage. In order to achieve the above object, thin film transistors including oxide semiconductor layers with different thicknesses may be formed over the same substrate, and the thin film transistors whose threshold voltages are controlled by the thicknesses of the oxide semiconductor layers may be used to form a logic circuit. In addition, by using an oxide semiconductor film in contact with an oxide insulating film formed after dehydration or dehydrogenation treatment, a change in threshold voltage over time is suppressed and the reliability of a logic circuit can be improved.

摘要翻译： 目的是获得使用氧化物半导体的薄膜晶体管的期望阈值电压。 另一个目的是抑制阈值电压随时间的变化。 具体地，目的是将薄膜晶体管施加到使用具有期望阈值电压的晶体管形成的逻辑电路。 为了实现上述目的，可以在相同的衬底上形成包括具有不同厚度的氧化物半导体层的薄膜晶体管，并且其阈值电压由氧化物半导体层的厚度控制的薄膜晶体管可以用于形成 逻辑电路。 此外，通过使用与脱水或脱氢处理之后形成的氧化物绝缘膜接触的氧化物半导体膜，抑制了阈值电压随时间的变化，并且可以提高逻辑电路的可靠性。

公开(公告)号：US08174021B2

公开(公告)日：2012-05-08

申请号：US12695179

申请日：2010-01-28

申请人： Yoshiaki Oikawa ,  Hotaka Maruyama ,  Hiromichi Godo ,  Daisuke Kawae ,  Shunpei Yamazaki

发明人： Yoshiaki Oikawa ,  Hotaka Maruyama ,  Hiromichi Godo ,  Daisuke Kawae ,  Shunpei Yamazaki

IPC分类号： H01L27/14

CPC分类号： H01L27/1225 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/156 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

摘要： An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.

摘要翻译： 本发明的目的是提供一种具有使用氧化物半导体层的具有优异电特性的薄膜晶体管的半导体器件。 包括SiOX的In-Sn-O系氧化物半导体层用于沟道形成区域。 为了降低包含SiOX的In-Sn-O系氧化物半导体层与由电阻低的金属材料形成的布线层之间的接触电阻，在源电极层或漏极之间形成源极区或漏极区 层和包含SiOX的In-Sn-O系氧化物半导体层。 使用不包含SiOX的In-Sn-O系氧化物半导体层来形成源极区域或漏极区域以及像素区域。

公开(公告)号：US08120030B2

公开(公告)日：2012-02-21

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US07868328B2

公开(公告)日：2011-01-11

申请号：US12362462

申请日：2009-01-29

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Tetsuji Yamaguchi ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Tetsuji Yamaguchi ,  Hiromichi Godo

IPC分类号： H01L29/786

CPC分类号： H01L27/127 ,  H01L24/32 ,  H01L24/73 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1214 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627 ,  H01L2029/7863 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01014

摘要： The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.

摘要翻译： 本发明提供一种能够大规模生产的半导体器件和该半导体器件的制造方法。 本发明还提供了使用极薄集成电路的半导体器件和半导体器件的制造方法。 此外，本发明提供一种半导体器件的低功耗半导体器件和制造方法。 根据本发明的一个方面，提供了一种在绝缘表面上具有半导体非易失性存储元件晶体管的半导体器件，其中存储晶体管的浮置栅电极由多个导电粒子或半导体粒子形成。

公开(公告)号：US07786485B2

公开(公告)日：2010-08-31

申请号：US12390144

申请日：2009-02-20

申请人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15

CPC分类号： H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.

摘要翻译： 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于 栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上设置有间隔; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。