公开(公告)号：US09276005B1

公开(公告)日：2016-03-01

申请号：US14560475

申请日：2014-12-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.

Abstract translation: 存储单元包括在其中具有沟道区域的衬底中的源极和漏极区域，源极区域上的擦除栅极，在第一沟道区域部分上的浮动栅极，浮置栅极上的控制栅极以及第二沟道区域上的字线栅极 通道区域部分。 第一逻辑器件包括衬底中的第二源极和漏极区域，在第一逻辑门之下具有第二沟道区域。 第二逻辑器件包括衬底中的第三源极和漏极区域，在第二逻辑门极之间具有第三沟道区域。 字线栅极和第一和第二逻辑门包括相同的导电金属材料。 第二逻辑门通过第一和第二绝缘与第三沟道区绝缘。 第一逻辑门通过第二绝缘而与第二沟道区绝缘，而不是通过第一绝缘。

公开(公告)号：US09123431B2

公开(公告)日：2015-09-01

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

公开(公告)号：US20140269058A1

公开(公告)日：2014-09-18

申请号：US14214097

申请日：2014-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

IPC: G11C16/34 ,  G11C16/12

CPC classification number: G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

Abstract translation: 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。

公开(公告)号：US11737266B2

公开(公告)日：2023-08-22

申请号：US17339880

申请日：2021-06-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Guo Xiang Song ,  Chunming Wang ,  Leo Xing ,  Xian Liu ,  Nhan Do

IPC: H01L27/088 ,  H10B41/41

CPC classification number: H10B41/41

Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.

公开(公告)号：US20230189520A1

公开(公告)日：2023-06-15

申请号：US18103265

申请日：2023-01-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Guo Xiang Song ,  Chunming Wang ,  Leo Xing ,  Xian Liu ,  Nhan Do

IPC: H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7883 ,  H10B41/30

Abstract: A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.

公开(公告)号：US20220208277A1

公开(公告)日：2022-06-30

申请号：US17199383

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Xian Liu ,  Chunming Wang ,  Nhan Do ,  Hieu Van Tran

IPC: G11C16/26 ,  H03K19/20 ,  G06F11/10

Abstract: Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.

公开(公告)号：US20220102517A1

公开(公告)日：2022-03-31

申请号：US17165934

申请日：2021-02-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: H01L29/423 ,  G11C16/04 ,  H01L29/66 ,  H01L29/788

Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

公开(公告)号：US20210398995A1

公开(公告)日：2021-12-23

申请号：US17129865

申请日：2020-12-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jack Sun ,  Chunming Wang ,  Xian Liu ,  Andy Yang ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/423 ,  H01L29/66

Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.

公开(公告)号：US11183506B2

公开(公告)日：2021-11-23

申请号：US17005139

申请日：2020-08-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Xian Liu ,  Feng Zhou ,  Parviz Ghazavi ,  Steven Lemke ,  Nhan Do

IPC: H01L27/11536 ,  H01L29/66 ,  H01L21/3205 ,  H01L27/11521 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/265 ,  H01L21/321

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

公开(公告)号：US10833178B2

公开(公告)日：2020-11-10

申请号：US16576370

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.