公开(公告)号：US06955952B2

公开(公告)日：2005-10-18

申请号：US10383709

申请日：2003-03-07

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于双轴拉伸污染增强电子迁移率的硅层中。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

公开(公告)号：US20050170577A1

公开(公告)日：2005-08-04

申请号：US10769316

申请日：2004-01-30

申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/338

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532

摘要： A strained silicon layer fabrication employs a substrate having successively formed thereover: (1) a first silicon-germanium alloy material layer; (2) a first silicon layer; (3) a second silicon-germanium alloy material layer; and (4) a second silicon layer. Within the fabrication each of the first silicon-germanium alloy layer and the second silicon-germanium alloy layer is formed of a thickness less than a threshold thickness for dislocation defect formation, such as to provide attenuated dislocation defect formation within the strained silicon layer fabrication.

摘要翻译： 应变硅层制造采用在其上依次形成的基板：（1）第一硅 - 锗合金材料层; （2）第一硅层; （3）第二硅 - 锗合金材料层; 和（4）第二硅层。 在制造中，第一硅 - 锗合金层和第二硅 - 锗合金层中的每一个由低于用于位错缺陷形成的阈值厚度的厚度形成，例如在应变硅层制造中提供衰减的位错缺陷形成。

公开(公告)号：US20050095869A1

公开(公告)日：2005-05-05

申请号：US10701825

申请日：2003-11-05

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 通过使用包含氟和氧的高密度，高自由基浓度的等离子体蚀刻底部蚀刻停止层来去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，以最小化底部的铜的反溅射 蚀刻停止层和由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US06793797B2

公开(公告)日：2004-09-21

申请号：US10106733

申请日：2002-03-26

申请人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Winston Shue ,  Mong-Song Liang

发明人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Winston Shue ,  Mong-Song Liang

IPC分类号： C25D518

CPC分类号： H01L21/2885 ,  B23H5/08 ,  C25D5/18 ,  C25D7/123 ,  H01L21/32125 ,  H01L21/76877

摘要： A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.

摘要翻译： 一种用于交替电沉积和电机械抛光以选择性地用金属填充半导体特征的方法，包括：a）提供以间隔开的关系设置的阳极组件和半导体晶片，所述阳极组件和半导体晶片在半导体晶片之间包括电解质，所述电解质包括包括各向异性蚀刻特征 安排电沉积过程; b）在阳极组件和半导体晶片之间施加电位以在第一电流密度下引起电解质流动，以将金属填充部分电沉积到工艺表面上; c）逆转电位以在第二电流密度下反转电解质流动，以在电抛光过程中电镀处理表面; 以及d）依次重复步骤b和c以电沉积至少第二金属填充部分以基本上填充各向异性蚀刻的特征。

公开(公告)号：US06600186B1

公开(公告)日：2003-07-29

申请号：US09670328

申请日：2000-09-27

申请人： Jin-Yuan Lee ,  Mong-Song Liang

发明人： Jin-Yuan Lee ,  Mong-Song Liang

IPC分类号： H01L27108

CPC分类号： H01L27/10897 ,  G11C11/4074 ,  G11C2207/104 ,  H01L21/823878

摘要： Embedded DRAM cells within an ASIC having a pass transistor with a gate oxide having a thickness equal to the thickness of the gate oxide of the logic core. This allows the embedded DRAM cell to be activated by signals having voltage levels equal to the voltage levels created by the logic core. If the gate oxide has a thickness that is equal to the gate oxide thickness of the peripheral circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by peripheral circuits, and signal provided by the bit line voltage generator has voltage levels equal to those provided by logic circuits within the logic core. If the gate oxide has a thickness that is equal to the thickness of the gate oxide of the logic circuits, a signal provided by the word line voltage generator has voltage levels equal to those provided by the logic circuits, and the bit line voltage generator has voltage levels equal to those provided by the logic circuits.

摘要翻译： ASIC内的嵌入式DRAM单元具有带栅极氧化物的传输晶体管，其厚度等于逻辑核心的栅极氧化物的厚度。 这允许嵌入式DRAM单元由具有等于逻辑核心产生的电压电平的信号激活。 如果栅极氧化物的厚度等于外围电路的栅极氧化物厚度，则由字线电压发生器提供的信号的电压电平等于外围电路提供的电压，并且由位线电压发生器提供的信号具有 电压电平等于逻辑电路内的逻辑电路。 如果栅极氧化物的厚度等于逻辑电路的栅极氧化物的厚度，则由字线电压发生器提供的信号的电压电平等于由逻辑电路提供的电压，并且位线电压发生器具有 电压电平等于由逻辑电路提供的电压。

公开(公告)号：US06590344B2

公开(公告)日：2003-07-08

申请号：US10003492

申请日：2001-11-20

申请人： Shun-Jan Tao ,  Huan-Just Lin ,  Mong-Song Liang

发明人： Shun-Jan Tao ,  Huan-Just Lin ,  Mong-Song Liang

IPC分类号： H01J724

CPC分类号： C23C16/45574 ,  C23C16/45565 ,  H01J37/3244 ,  H01J37/32449

摘要： A gas distribution system for improving asymmetric etching and deposition control over a substrate diameter in a plasma reactor including a plasma reactor chamber further including a substrate holder for holding a substrate surface disposed in a lower portion of said plasma reactor; at least one gas distributor disposed within the plasma reactor chamber for distributing reactant gases where at least one gas distributor including a plurality of gas feed zones in communication with at least one gas source for selectively delivering a gas flow independently to at least one of the plurality of gas feed zones.

摘要翻译： 一种气体分配系统，用于在包括等离子体反应器室的等离子体反应器室中进一步包括用于保持设置在所述等离子体反应器的下部中的基板表面的基板保持器，用于改善在等离子体反应器中的基板直径上的 设置在等离子体反应器室内的至少一个气体分配器，用于分配反应气体，其中至少一个气体分配器包括与至少一个气体源连通的多个气体进料区，用于选择性地将气流独立地输送到多个 的供气区。

公开(公告)号：US06548856B1

公开(公告)日：2003-04-15

申请号：US09583403

申请日：2000-05-31

申请人： Chrong-Jung Lin ,  Shui-Hung Chen ,  Mong-Song Liang

发明人： Chrong-Jung Lin ,  Shui-Hung Chen ,  Mong-Song Liang

IPC分类号： H01L29788

CPC分类号： H01L27/11556

摘要： A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

摘要翻译： 形成垂直晶体管存储器件的方法包括以下处理步骤。 在形成沟槽之前，在行之间形成FOX区域。 然后在半导体衬底中形成具有侧壁和底部的一组沟槽，其中侧壁具有阈值注入区域。 在衬底的表面附近形成掺杂的漏极区域，并且在沟槽底部的器件的底部中的掺杂源极区域之间具有相反掺杂的沟道区域。 在包括沟槽的衬底上形成隧道氧化物层。 在沟槽上延伸的隧道氧化物层上形成掺杂多晶硅的覆盖薄的浮动栅极层。 蚀刻漂浮栅极层，沿着沟槽的侧壁留下浮动栅极层的直立浮栅条。 在浮栅层和隧道氧化物层之上形成由ONO组成的电极间电介质层。 在电极间电介质层上形成掺杂多晶硅的覆盖薄的控制栅极层。 将控制栅层图案化为控制栅电极。 形成与控制栅电极的侧壁相邻的间隔物。

公开(公告)号：US6083795A

公开(公告)日：2000-07-04

申请号：US20497

申请日：1998-02-09

申请人： Mong-Song Liang ,  Ching-Hsiang Hsu

发明人： Mong-Song Liang ,  Ching-Hsiang Hsu

IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L21/26586 ,  H01L21/76216 ,  H01L29/1033

摘要： The present invention provides a method of manufacturing MOS device having threshold voltage adjustment region 28 ormed using a large angled implant. The invention's angled implant serves as both (a) a Vt adjustment I/I and (b) a Channel stop I/I by (1) increasing the threshold voltage (Vt) and (2) reducing the leakage current. The method comprises forming spaced field oxide regions having bird's beaks on a semiconductor substrate. A field implant is performed using the spaced field oxide regions as an implant mask formed a deep channel stop region 24. Next, a sacrificial oxide layer 20 is formed over the resultant surface. In a critical step, a threshold voltage adjustment region 28 is formed by performing a large angled implant of a p-type ions. The p-type ions into are implanted into the channel region 19 and under the bird's beak 18 such that the threshold voltage is higher under the bird's beak than in the channel region 19. A MOS transistor is then formed over the channel region. The large angled threshold voltage implant of the present invention eliminates the reverse narrow width effect (e.g., reduced threshold voltage (Vt) and increased leakage currents).

摘要翻译： 本发明提供了一种制造具有阈值电压调节区域28的MOS器件的方法，所述阈值电压调节区域28使用大角度植入物进行。 本发明的倾斜注入用作（a）Vt调节I / I和（b）通道停止I / I，通过（1）增加阈值电压（Vt）和（2）减小漏电流。 该方法包括在半导体衬底上形成具有鸟喙的间隔的场氧化物区域。 使用间隔的场氧化物区域作为形成深沟道停止区域24的注入掩模来执行场注入。接下来，在所得表面上形成牺牲氧化物层20。 在关键步骤中，通过执行p型离子的大角度注入来形成阈值电压调整区域28。 将p型离子注入到通道区域19中并且在鸟的嘴部18下方，使得阈值电压在鸟喙下比通道区域19中更高。然后在沟道区域上形成MOS晶体管。 本发明的大角度阈值电压注入消除了反向窄宽度效应（例如，降低的阈值电压（Vt）和增加的漏电流）。

公开(公告)号：US6001731A

公开(公告)日：1999-12-14

申请号：US682457

申请日：1996-07-17

申请人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

发明人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76819 ,  H01L21/31053

摘要： A method for providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer with non-planar surface topography; ii) chemical-mechanical polishing the first insulating layer; and iii) deposition of another polysilicon layer of second thickness to prevent the barely exposed or exposed underlying polysilicon from shorting to the next polysilicon or metal level of interconnects.

摘要翻译： 一种用于提供用于防止多晶硅和多金属级电短路的化学机械抛光平面化工艺的方法，其中简要地描述了以下顺序的处理步骤：i）在具有非平面表面的器件晶片上提供第一厚度的绝缘层 地形; ii）化学机械抛光第一绝缘层; 以及iii）沉积第二厚度的另一多晶硅层，以防止几乎暴露或暴露的下面的多晶硅短路到下一个多晶硅或金属互连级。

公开(公告)号：US5877523A

公开(公告)日：1999-03-02

申请号：US974459

申请日：1997-11-20

申请人： Mong-Song Liang ,  Di-Son Kuo ,  Ching-Hsiang Hsu ,  Ruei-Ling Lin

发明人： Mong-Song Liang ,  Di-Son Kuo ,  Ching-Hsiang Hsu ,  Ruei-Ling Lin

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/788

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C16/0458 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7887 ,  G11C2211/5612

摘要： A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes. There are source/drain regions in the substrate self-aligned with the control gate electrode.

摘要翻译： 半导体存储器件形成在掺杂半导体衬底上，并被掺杂的第一多晶硅层依次覆盖的隧道氧化物层覆盖。 将第一多晶硅层图案化成一对浮栅电极。 电极间电介质层覆盖浮置栅电极，浮置栅电极的侧壁和隧道氧化物的边缘在浮栅电极下方。 第二多晶硅层覆盖在电极之间的电介质层上，又由硅化钨层覆盖。 第二介电层覆盖硅化钨层。 跨越一对浮置栅电极的控制栅极电极由第二多晶硅层形成，硅化钨和第一和第二电介质层图案化成栅电极堆叠，提供横跨该对浮置栅电极的控制栅电极。 衬底中的源极/漏极区域与控制栅电极自对准。