公开(公告)号：US12243849B2

公开(公告)日：2025-03-04

申请号：US17491378

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chittranjan Mohan Gupta ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Jie Chen ,  Tianyi Luo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

公开(公告)号：US12224480B2

公开(公告)日：2025-02-11

申请号：US17736653

申请日：2022-05-04

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q1/22 ,  H01L23/66 ,  H01Q9/04 ,  H01Q13/02 ,  H01Q19/10

Abstract: An example semiconductor package comprises a patch antenna formed in a first conductor layer of a multilayer package substrate. The multilayer package substrate comprises conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers. The multilayer package substrate has a board side surface opposite a device side surface. The semiconductor package further comprises a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna. An antenna horn is mounted to the device side surface and aligned with the patch antenna using a mounting structure. The semiconductor package further comprises a reflector formed on a second conductor layer in the multilayer package substrate. The second conductor layer is positioned closer to the board side surface of the multilayer package substrate compared to the patch antenna.

公开(公告)号：US20240258704A1

公开(公告)日：2024-08-01

申请号：US18104124

申请日：2023-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Bakshi

IPC: H01Q13/00 ,  H01Q1/48 ,  H01Q9/04

CPC classification number: H01Q13/00 ,  H01Q1/48 ,  H01Q9/0407

Abstract: A microelectronic package includes a waveguide radiation receiver formed in a first conductor layer of a multilayer package substrate, the multilayer package substrate comprising the first conductor layer spaced from a second conductor layer by a dielectric layer. The microelectronic package further includes a tubular waveguide mounted to the multilayer package substrate such that a central aperture of the tubular waveguide is over the waveguide radiation receiver, and a feed line coupling the waveguide radiation receiver to a transmitter-receiver, the feed line including a conductive via traversing the dielectric layer electrically coupling a first portion of the feed line in the first conductor layer to a second portion of the feed line in the second conductor layer, the first portion adjacent the waveguide radiation receiver, and the second portion adjacent the transmitter-receiver.

公开(公告)号：US20240178163A1

公开(公告)日：2024-05-30

申请号：US18072026

申请日：2022-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen M. Murugan ,  Aditya Nitin Jogalekar

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/06 ,  H01L23/31 ,  H01Q5/25 ,  H01Q9/28 ,  H01Q13/10

CPC classification number: H01L23/66 ,  H01L23/06 ,  H01L23/3107 ,  H01L24/20 ,  H01Q5/25 ,  H01Q9/285 ,  H01Q13/106 ,  H01L2223/6677 ,  H01L2224/221

Abstract: An example semiconductor package comprises a semiconductor die having a top surface, a passivation layer over the top surface, a first metal layer on the first passivation layer, an antenna formed in the first metal layer and offset from the semiconductor die, the antenna having a slot bow-tie configuration, a transmission line formed in the first metal layer, the transmission line coupling the semiconductor die to the antenna, and an insulating material separating the first metal layer from a second metal layer, the second metal layer configured to function as a ground reflector for the antenna. The second metal layer may extend below the antenna and the semiconductor die.

公开(公告)号：US11978709B2

公开(公告)日：2024-05-07

申请号：US17752037

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/495 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683 ,  H01L25/16

CPC classification number: H01L23/60 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/28 ,  H01L24/82 ,  H01L33/005 ,  H01L33/62 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/25 ,  H01L25/167 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US20240072025A1

公开(公告)日：2024-02-29

申请号：US17893312

申请日：2022-08-23

Applicant: Texas Instruments Incorporated

Inventor： Rajen M. Murugan ,  Yiqi Tang ,  Jie Chen ,  Ramlah Abdul Razak

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L25/165 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48195 ,  H01L2224/73265 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/17787 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025

Abstract: An example semiconductor package comprises a ceramic header having a first open space separated from a second open space by a ceramic barrier. A first heat sink is attached to a bottom of the ceramic header below the first open area. A first integrated circuit (IC) die is mounted on the first heat sink. A second heat sink is attached to a bottom of the ceramic header below the second open area. A second IC die is mounted on the second heat sink. A capacitive interface is disposed in the ceramic barrier between the first IC die and the second IC die. The capacitive has a plurality of capacitive elements alternating with a plurality of shielding elements. The capacitive elements are tunable over a range of capacitive values.

公开(公告)号：US11881460B2

公开(公告)日：2024-01-23

申请号：US18172208

申请日：2023-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Li Jiang ,  Rajen Manicon Murugan

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/58 ,  H01L21/50 ,  H01L21/52

CPC classification number: H01L23/585 ,  H01L21/50 ,  H01L21/52 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564

Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

公开(公告)号：US20240006267A1

公开(公告)日：2024-01-04

申请号：US17809808

申请日：2022-06-29

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Yiqi Tang ,  Jie Chen ,  Rajen M. Murugan

IPC: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/4882 ,  H01L24/16

Abstract: An example semiconductor package comprises a ceramic header having a top surface and a cavity formed within the ceramic header. The cavity is open at the top surface. A semiconductor die is mounted within the cavity of the ceramic header. A lid structure is coupled to the top surface of the ceramic header. The lid structure and ceramic header form a portion of a package enclosing the semiconductor die. One or more silver tubes are in contact with a first surface of the semiconductor die and with a first surface of the lid structure. A seal ring is located between the top surface of the ceramic header and the lid structure. The seal ring couples the lid structure to the ceramic header. The one or more silver tubes are hollow and filled with a getter material.

公开(公告)号：US20230207430A1

公开(公告)日：2023-06-29

申请号：US18177273

申请日：2023-03-02

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49534 ,  H01L23/49589 ,  H01L23/49558 ,  H01L23/49575 ,  H01L21/565 ,  H01L21/563 ,  H01L21/4821 ,  H01L24/16 ,  H01L23/3107 ,  H01L2224/16245

Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

公开(公告)号：US11587899B2

公开(公告)日：2023-02-21

申请号：US16941818

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.