公开(公告)号：US12027423B2

公开(公告)日：2024-07-02

申请号：US17813850

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

公开(公告)号：US12022660B2

公开(公告)日：2024-06-25

申请号：US18447495

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/00 ,  H01L21/8234 ,  H01L23/522 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/40 ,  H01L21/823475 ,  H01L23/5226 ,  H10B51/30

Abstract: Semiconductor devices and methods of manufacture are provided wherein a ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array. A through via is formed using the same processes as the processes used to form individual memory cells within the ferroelectric random access memory array.

公开(公告)号：US12015031B2

公开(公告)日：2024-06-18

申请号：US17961949

申请日：2022-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Szu-Ping Lee ,  Che-Hao Chang ,  Chun-Heng Chen ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/94 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L31/062

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

公开(公告)号：US20240177998A1

公开(公告)日：2024-05-30

申请号：US18435140

申请日：2024-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/28568 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.

公开(公告)号：US20240145250A1

公开(公告)日：2024-05-02

申请号：US18411197

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Han Chen ,  Tsung-Ju Chen ,  Ta-Hsiang Kung ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28141 ,  H01L21/0234 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

公开(公告)号：US11968838B2

公开(公告)日：2024-04-23

申请号：US17460569

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/06 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H01L29/78391 ,  H10B51/10

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

公开(公告)号：US11955370B2

公开(公告)日：2024-04-09

申请号：US17025528

申请日：2020-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Ting-Gang Chen ,  Sung-En Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui ,  Tai-Chun Huang ,  Chieh-Ping Wang

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76837 ,  H01L21/823481

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

公开(公告)号：US11916124B2

公开(公告)日：2024-02-27

申请号：US17717382

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L29/42392 ,  H01L29/401 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/0673 ,  H01L29/4908

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

公开(公告)号：US11916114B2

公开(公告)日：2024-02-27

申请号：US17854244

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/78696 ,  H01L21/823807

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US11901439B2

公开(公告)日：2024-02-13

申请号：US17815527

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/78696 ,  H01L21/823468

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.